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Anshuman Khandualwilldeacon
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arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruption
If a Cortex-A715 cpu sees a page mapping permissions change from executable to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers, on the next instruction abort caused by permission fault. Only user-space does executable to non-executable permission transition via mprotect() system call which calls ptep_modify_prot_start() and ptep_modify _prot_commit() helpers, while changing the page mapping. The platform code can override these helpers via __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION. Work around the problem via doing a break-before-make TLB invalidation, for all executable user space mappings, that go through mprotect() system call. This overrides ptep_modify_prot_start() and ptep_modify_prot_commit(), via defining HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION on the platform thus giving an opportunity to intercept user space exec mappings, and do the necessary TLB invalidation. Similar interceptions are also implemented for HugeTLB. Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: Jonathan Corbet <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Reviewed-by: Catalin Marinas <[email protected]> Signed-off-by: Anshuman Khandual <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
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Documentation/arm64/silicon-errata.rst

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@@ -120,6 +120,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |

arch/arm64/Kconfig

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@@ -972,6 +972,22 @@ config ARM64_ERRATUM_2457168
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If unsure, say Y.
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config ARM64_ERRATUM_2645198
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bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
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default y
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help
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This option adds the workaround for ARM Cortex-A715 erratum 2645198.
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If a Cortex-A715 cpu sees a page mapping permissions change from executable
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to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
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next instruction abort caused by permission fault.
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Only user-space does executable to non-executable permission transition via
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mprotect() system call. Workaround the problem by doing a break-before-make
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TLB invalidation, for all changes to executable user space mappings.
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If unsure, say Y.
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config CAVIUM_ERRATUM_22375
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bool "Cavium erratum 22375, 24313"
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default y

arch/arm64/include/asm/hugetlb.h

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@@ -49,6 +49,15 @@ extern pte_t huge_ptep_get(pte_t *ptep);
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void __init arm64_hugetlb_cma_reserve(void);
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#define huge_ptep_modify_prot_start huge_ptep_modify_prot_start
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extern pte_t huge_ptep_modify_prot_start(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep);
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#define huge_ptep_modify_prot_commit huge_ptep_modify_prot_commit
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extern void huge_ptep_modify_prot_commit(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep,
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pte_t old_pte, pte_t new_pte);
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#include <asm-generic/hugetlb.h>
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#endif /* __ASM_HUGETLB_H */

arch/arm64/include/asm/pgtable.h

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@@ -1093,6 +1093,15 @@ static inline bool pud_sect_supported(void)
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}
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#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
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#define ptep_modify_prot_start ptep_modify_prot_start
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extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep);
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#define ptep_modify_prot_commit ptep_modify_prot_commit
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extern void ptep_modify_prot_commit(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep,
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pte_t old_pte, pte_t new_pte);
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_PGTABLE_H */

arch/arm64/kernel/cpu_errata.c

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@@ -661,6 +661,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2645198
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{
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.desc = "ARM erratum 2645198",
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.capability = ARM64_WORKAROUND_2645198,
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ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A715)
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2077057
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{
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.desc = "ARM erratum 2077057",

arch/arm64/mm/hugetlbpage.c

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@@ -559,3 +559,24 @@ bool __init arch_hugetlb_valid_size(unsigned long size)
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{
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return __hugetlb_valid_size(size);
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}
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pte_t huge_ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
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{
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if (IS_ENABLED(CONFIG_ARM64_ERRATUM_2645198) &&
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cpus_have_const_cap(ARM64_WORKAROUND_2645198)) {
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/*
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* Break-before-make (BBM) is required for all user space mappings
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* when the permission changes from executable to non-executable
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* in cases where cpu is affected with errata #2645198.
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*/
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if (pte_user_exec(READ_ONCE(*ptep)))
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return huge_ptep_clear_flush(vma, addr, ptep);
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}
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return huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);
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}
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void huge_ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep,
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pte_t old_pte, pte_t pte)
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{
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set_huge_pte_at(vma->vm_mm, addr, ptep, pte);
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}

arch/arm64/mm/mmu.c

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@@ -1630,3 +1630,24 @@ static int __init prevent_bootmem_remove_init(void)
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}
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early_initcall(prevent_bootmem_remove_init);
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#endif
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pte_t ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
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{
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if (IS_ENABLED(CONFIG_ARM64_ERRATUM_2645198) &&
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cpus_have_const_cap(ARM64_WORKAROUND_2645198)) {
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/*
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* Break-before-make (BBM) is required for all user space mappings
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* when the permission changes from executable to non-executable
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* in cases where cpu is affected with errata #2645198.
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*/
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if (pte_user_exec(READ_ONCE(*ptep)))
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return ptep_clear_flush(vma, addr, ptep);
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}
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return ptep_get_and_clear(vma->vm_mm, addr, ptep);
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}
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void ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep,
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pte_t old_pte, pte_t pte)
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{
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set_pte_at(vma->vm_mm, addr, ptep, pte);
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}

arch/arm64/tools/cpucaps

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@@ -71,6 +71,7 @@ WORKAROUND_2038923
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WORKAROUND_2064142
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WORKAROUND_2077057
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WORKAROUND_2457168
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WORKAROUND_2645198
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WORKAROUND_2658417
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WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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WORKAROUND_TSB_FLUSH_FAILURE

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