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FlyGoatdlezcano
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clocksource/drivers/mips-gic-timer: Correct sched_clock width
Counter width of GIC is configurable and can be read from a register. Use width value from the register for sched_clock. Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Jiaxun Yang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Daniel Lezcano <[email protected]>
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drivers/clocksource/mips-gic-timer.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
2020
static int gic_timer_irq;
2121
static unsigned int gic_frequency;
22+
static unsigned int gic_count_width;
2223
static bool __read_mostly gic_clock_unstable;
2324

2425
static void gic_clocksource_unstable(char *reason);
@@ -186,15 +187,14 @@ static void gic_clocksource_unstable(char *reason)
186187

187188
static int __init __gic_clocksource_init(void)
188189
{
189-
unsigned int count_width;
190190
int ret;
191191

192192
/* Set clocksource mask. */
193-
count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
194-
count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
195-
count_width *= 4;
196-
count_width += 32;
197-
gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
193+
gic_count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
194+
gic_count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
195+
gic_count_width *= 4;
196+
gic_count_width += 32;
197+
gic_clocksource.mask = CLOCKSOURCE_MASK(gic_count_width);
198198

199199
/* Calculate a somewhat reasonable rating value. */
200200
if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ))
@@ -264,7 +264,7 @@ static int __init gic_clocksource_of_init(struct device_node *node)
264264
if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) {
265265
sched_clock_register(mips_cm_is64 ?
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gic_read_count_64 : gic_read_count_2x32,
267-
64, gic_frequency);
267+
gic_count_width, gic_frequency);
268268
}
269269

270270
return 0;

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