|
19 | 19 | static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
|
20 | 20 | static int gic_timer_irq;
|
21 | 21 | static unsigned int gic_frequency;
|
| 22 | +static unsigned int gic_count_width; |
22 | 23 | static bool __read_mostly gic_clock_unstable;
|
23 | 24 |
|
24 | 25 | static void gic_clocksource_unstable(char *reason);
|
@@ -186,15 +187,14 @@ static void gic_clocksource_unstable(char *reason)
|
186 | 187 |
|
187 | 188 | static int __init __gic_clocksource_init(void)
|
188 | 189 | {
|
189 |
| - unsigned int count_width; |
190 | 190 | int ret;
|
191 | 191 |
|
192 | 192 | /* Set clocksource mask. */
|
193 |
| - count_width = read_gic_config() & GIC_CONFIG_COUNTBITS; |
194 |
| - count_width >>= __ffs(GIC_CONFIG_COUNTBITS); |
195 |
| - count_width *= 4; |
196 |
| - count_width += 32; |
197 |
| - gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); |
| 193 | + gic_count_width = read_gic_config() & GIC_CONFIG_COUNTBITS; |
| 194 | + gic_count_width >>= __ffs(GIC_CONFIG_COUNTBITS); |
| 195 | + gic_count_width *= 4; |
| 196 | + gic_count_width += 32; |
| 197 | + gic_clocksource.mask = CLOCKSOURCE_MASK(gic_count_width); |
198 | 198 |
|
199 | 199 | /* Calculate a somewhat reasonable rating value. */
|
200 | 200 | if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ))
|
@@ -264,7 +264,7 @@ static int __init gic_clocksource_of_init(struct device_node *node)
|
264 | 264 | if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) {
|
265 | 265 | sched_clock_register(mips_cm_is64 ?
|
266 | 266 | gic_read_count_64 : gic_read_count_2x32,
|
267 |
| - 64, gic_frequency); |
| 267 | + gic_count_width, gic_frequency); |
268 | 268 | }
|
269 | 269 |
|
270 | 270 | return 0;
|
|
0 commit comments