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alexdeucheralexdeucher
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drm/amdgpu: add support for IP discovery gc_info table v2
Used on gfx9 based systems. Fixes incorrect CU counts reported in the kernel log. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1833 Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
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+103
-22
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2 files changed

+103
-22
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

Lines changed: 54 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -526,39 +526,71 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
526526
}
527527
}
528528

529+
union gc_info {
530+
struct gc_info_v1_0 v1;
531+
struct gc_info_v2_0 v2;
532+
};
533+
529534
int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
530535
{
531536
struct binary_header *bhdr;
532-
struct gc_info_v1_0 *gc_info;
537+
union gc_info *gc_info;
533538

534539
if (!adev->mman.discovery_bin) {
535540
DRM_ERROR("ip discovery uninitialized\n");
536541
return -EINVAL;
537542
}
538543

539544
bhdr = (struct binary_header *)adev->mman.discovery_bin;
540-
gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin +
545+
gc_info = (union gc_info *)(adev->mman.discovery_bin +
541546
le16_to_cpu(bhdr->table_list[GC].offset));
542-
543-
adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);
544-
adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
545-
le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
546-
adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
547-
adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
548-
adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);
549-
adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
550-
adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);
551-
adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);
552-
adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);
553-
adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer);
554-
adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size);
555-
adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd);
556-
adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu);
557-
adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size);
558-
adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) /
559-
le32_to_cpu(gc_info->gc_num_sa_per_se);
560-
adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc);
561-
547+
switch (gc_info->v1.header.version_major) {
548+
case 1:
549+
adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
550+
adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
551+
le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
552+
adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
553+
adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
554+
adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
555+
adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
556+
adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
557+
adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
558+
adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
559+
adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
560+
adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
561+
adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
562+
adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
563+
adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
564+
adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
565+
le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
566+
adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
567+
break;
568+
case 2:
569+
adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
570+
adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
571+
adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
572+
adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
573+
adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
574+
adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
575+
adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
576+
adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
577+
adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
578+
adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
579+
adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
580+
adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
581+
adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
582+
adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
583+
adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
584+
le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
585+
adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
586+
break;
587+
default:
588+
dev_err(adev->dev,
589+
"Unhandled GC info table %d.%d\n",
590+
gc_info->v1.header.version_major,
591+
gc_info->v1.header.version_minor);
592+
return -EINVAL;
593+
}
562594
return 0;
563595
}
564596

‎drivers/gpu/drm/amd/include/discovery.h

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,6 +143,55 @@ struct gc_info_v1_0 {
143143
uint32_t gc_num_gl2a;
144144
};
145145

146+
struct gc_info_v1_1 {
147+
struct gpu_info_header header;
148+
149+
uint32_t gc_num_se;
150+
uint32_t gc_num_wgp0_per_sa;
151+
uint32_t gc_num_wgp1_per_sa;
152+
uint32_t gc_num_rb_per_se;
153+
uint32_t gc_num_gl2c;
154+
uint32_t gc_num_gprs;
155+
uint32_t gc_num_max_gs_thds;
156+
uint32_t gc_gs_table_depth;
157+
uint32_t gc_gsprim_buff_depth;
158+
uint32_t gc_parameter_cache_depth;
159+
uint32_t gc_double_offchip_lds_buffer;
160+
uint32_t gc_wave_size;
161+
uint32_t gc_max_waves_per_simd;
162+
uint32_t gc_max_scratch_slots_per_cu;
163+
uint32_t gc_lds_size;
164+
uint32_t gc_num_sc_per_se;
165+
uint32_t gc_num_sa_per_se;
166+
uint32_t gc_num_packer_per_sc;
167+
uint32_t gc_num_gl2a;
168+
uint32_t gc_num_tcp_per_sa;
169+
uint32_t gc_num_sdp_interface;
170+
uint32_t gc_num_tcps;
171+
};
172+
173+
struct gc_info_v2_0 {
174+
struct gpu_info_header header;
175+
176+
uint32_t gc_num_se;
177+
uint32_t gc_num_cu_per_sh;
178+
uint32_t gc_num_sh_per_se;
179+
uint32_t gc_num_rb_per_se;
180+
uint32_t gc_num_tccs;
181+
uint32_t gc_num_gprs;
182+
uint32_t gc_num_max_gs_thds;
183+
uint32_t gc_gs_table_depth;
184+
uint32_t gc_gsprim_buff_depth;
185+
uint32_t gc_parameter_cache_depth;
186+
uint32_t gc_double_offchip_lds_buffer;
187+
uint32_t gc_wave_size;
188+
uint32_t gc_max_waves_per_simd;
189+
uint32_t gc_max_scratch_slots_per_cu;
190+
uint32_t gc_lds_size;
191+
uint32_t gc_num_sc_per_se;
192+
uint32_t gc_num_packer_per_sc;
193+
};
194+
146195
typedef struct harvest_info_header {
147196
uint32_t signature; /* Table Signature */
148197
uint32_t version; /* Table Version */

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