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sunyealkrzk
sunyeal
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krzk
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clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support
Register compatible and cmu_info data to support clocks. CMU_PERIC1, this provides clocks for USI09 ~ USI17, USI_I2C and USI_I3C. CMU_MISC, this provides clocks for MISC, GIC and OTP. CMU_HSI0, this provides clocks for PCIE. CMU_HSI1, this provides clocks for USB and MMC. Signed-off-by: Sunyeal Hong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
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‎drivers/clk/samsung/clk-exynosautov920.c‎

Lines changed: 289 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,10 @@
1919
/* NOTE: Must be equal to the last clock ID increased by one */
2020
#define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
2121
#define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
22+
#define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1)
23+
#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
24+
#define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1)
25+
#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1)
2226

2327
/* ---- CMU_TOP ------------------------------------------------------------ */
2428

@@ -974,6 +978,8 @@ static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initcon
974978
"mout_shared5_pll", 1, 3, 0),
975979
FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4",
976980
"mout_shared5_pll", 1, 4, 0),
981+
FFACTOR(DOUT_TCXO_DIV2, "dout_tcxo_div2",
982+
"oscclk", 1, 2, 0),
977983
};
978984

979985
static const struct samsung_cmu_info top_cmu_info __initconst = {
@@ -1139,6 +1145,277 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
11391145
.clk_name = "noc",
11401146
};
11411147

1148+
/* ---- CMU_PERIC1 --------------------------------------------------------- */
1149+
1150+
/* Register Offset definitions for CMU_PERIC1 (0x10C00000) */
1151+
#define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x600
1152+
#define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x610
1153+
#define CLK_CON_MUX_MUX_CLK_PERIC1_I3C 0x1000
1154+
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x1004
1155+
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1008
1156+
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x100c
1157+
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI 0x1010
1158+
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI 0x1014
1159+
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI 0x1018
1160+
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI 0x101c
1161+
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI 0x1020
1162+
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI 0x1024
1163+
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1028
1164+
#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
1165+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1804
1166+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
1167+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
1168+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
1169+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
1170+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI 0x1818
1171+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI 0x181c
1172+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820
1173+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824
1174+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1828
1175+
1176+
static const unsigned long peric1_clk_regs[] __initconst = {
1177+
PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
1178+
PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER,
1179+
CLK_CON_MUX_MUX_CLK_PERIC1_I3C,
1180+
CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
1181+
CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
1182+
CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
1183+
CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI,
1184+
CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI,
1185+
CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI,
1186+
CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI,
1187+
CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI,
1188+
CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI,
1189+
CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
1190+
CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
1191+
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1192+
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1193+
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1194+
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
1195+
CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
1196+
CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
1197+
CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
1198+
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
1199+
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
1200+
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
1201+
};
1202+
1203+
/* List of parent clocks for Muxes in CMU_PERIC1 */
1204+
PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
1205+
PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_clkcmu_peric1_noc" };
1206+
PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
1207+
1208+
static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
1209+
MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
1210+
mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
1211+
MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user",
1212+
mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1),
1213+
/* USI09 ~ USI17 */
1214+
MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
1215+
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
1216+
MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
1217+
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
1218+
MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
1219+
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
1220+
MUX(CLK_MOUT_PERIC1_USI12_USI, "mout_peric1_usi12_usi",
1221+
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1),
1222+
MUX(CLK_MOUT_PERIC1_USI13_USI, "mout_peric1_usi13_usi",
1223+
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1),
1224+
MUX(CLK_MOUT_PERIC1_USI14_USI, "mout_peric1_usi14_usi",
1225+
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1),
1226+
MUX(CLK_MOUT_PERIC1_USI15_USI, "mout_peric1_usi15_usi",
1227+
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1),
1228+
MUX(CLK_MOUT_PERIC1_USI16_USI, "mout_peric1_usi16_usi",
1229+
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1),
1230+
MUX(CLK_MOUT_PERIC1_USI17_USI, "mout_peric1_usi17_usi",
1231+
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1),
1232+
/* USI_I2C */
1233+
MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
1234+
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
1235+
/* USI_I3C */
1236+
MUX(CLK_MOUT_PERIC1_I3C, "mout_peric1_i3c",
1237+
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1),
1238+
};
1239+
1240+
static const struct samsung_div_clock peric1_div_clks[] __initconst = {
1241+
/* USI09 ~ USI17 */
1242+
DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
1243+
"mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1244+
0, 4),
1245+
DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
1246+
"mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1247+
0, 4),
1248+
DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
1249+
"mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1250+
0, 4),
1251+
DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
1252+
"mout_peric1_usi12_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
1253+
0, 4),
1254+
DIV(CLK_DOUT_PERIC1_USI13_USI, "dout_peric1_usi13_usi",
1255+
"mout_peric1_usi13_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
1256+
0, 4),
1257+
DIV(CLK_DOUT_PERIC1_USI14_USI, "dout_peric1_usi14_usi",
1258+
"mout_peric1_usi14_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
1259+
0, 4),
1260+
DIV(CLK_DOUT_PERIC1_USI15_USI, "dout_peric1_usi15_usi",
1261+
"mout_peric1_usi15_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
1262+
0, 4),
1263+
DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
1264+
"mout_peric1_usi16_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
1265+
0, 4),
1266+
DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
1267+
"mout_peric1_usi17_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
1268+
0, 4),
1269+
/* USI_I2C */
1270+
DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
1271+
"mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
1272+
/* USI_I3C */
1273+
DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c",
1274+
"mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
1275+
};
1276+
1277+
static const struct samsung_cmu_info peric1_cmu_info __initconst = {
1278+
.mux_clks = peric1_mux_clks,
1279+
.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
1280+
.div_clks = peric1_div_clks,
1281+
.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
1282+
.nr_clk_ids = CLKS_NR_PERIC1,
1283+
.clk_regs = peric1_clk_regs,
1284+
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
1285+
.clk_name = "noc",
1286+
};
1287+
1288+
/* ---- CMU_MISC --------------------------------------------------------- */
1289+
1290+
/* Register Offset definitions for CMU_MISC (0x10020000) */
1291+
#define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER 0x600
1292+
#define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
1293+
#define CLK_CON_DIV_CLKCMU_OTP 0x1800
1294+
#define CLK_CON_DIV_DIV_CLK_MISC_NOCP 0x1804
1295+
#define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2 0x1808
1296+
1297+
static const unsigned long misc_clk_regs[] __initconst = {
1298+
PLL_CON0_MUX_CLKCMU_MISC_NOC_USER,
1299+
CLK_CON_MUX_MUX_CLK_MISC_GIC,
1300+
CLK_CON_DIV_CLKCMU_OTP,
1301+
CLK_CON_DIV_DIV_CLK_MISC_NOCP,
1302+
CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2,
1303+
};
1304+
1305+
/* List of parent clocks for Muxes in CMU_MISC */
1306+
PNAME(mout_misc_noc_user_p) = { "oscclk", "dout_clkcmu_misc_noc" };
1307+
PNAME(mout_misc_gic_p) = { "dout_misc_nocp", "oscclk" };
1308+
1309+
static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
1310+
MUX(CLK_MOUT_MISC_NOC_USER, "mout_misc_noc_user",
1311+
mout_misc_noc_user_p, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 4, 1),
1312+
MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic",
1313+
mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1),
1314+
};
1315+
1316+
static const struct samsung_div_clock misc_div_clks[] __initconst = {
1317+
DIV(CLK_DOUT_MISC_NOCP, "dout_misc_nocp",
1318+
"mout_misc_noc_user", CLK_CON_DIV_DIV_CLK_MISC_NOCP,
1319+
0, 3),
1320+
};
1321+
1322+
static const struct samsung_fixed_factor_clock misc_fixed_factor_clks[] __initconst = {
1323+
FFACTOR(CLK_DOUT_MISC_OTP, "dout_misc_otp",
1324+
"oscclk", 1, 10, 0),
1325+
FFACTOR(CLK_DOUT_MISC_OSC_DIV2, "dout_misc_osc_div2",
1326+
"oscclk", 1, 2, 0),
1327+
};
1328+
1329+
static const struct samsung_cmu_info misc_cmu_info __initconst = {
1330+
.mux_clks = misc_mux_clks,
1331+
.nr_mux_clks = ARRAY_SIZE(misc_mux_clks),
1332+
.div_clks = misc_div_clks,
1333+
.nr_div_clks = ARRAY_SIZE(misc_div_clks),
1334+
.fixed_factor_clks = misc_fixed_factor_clks,
1335+
.nr_fixed_factor_clks = ARRAY_SIZE(misc_fixed_factor_clks),
1336+
.nr_clk_ids = CLKS_NR_MISC,
1337+
.clk_regs = misc_clk_regs,
1338+
.nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
1339+
.clk_name = "noc",
1340+
};
1341+
1342+
/* ---- CMU_HSI0 --------------------------------------------------------- */
1343+
1344+
/* Register Offset definitions for CMU_HSI0 (0x16000000) */
1345+
#define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x600
1346+
#define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB 0x1800
1347+
1348+
static const unsigned long hsi0_clk_regs[] __initconst = {
1349+
PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER,
1350+
CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
1351+
};
1352+
1353+
/* List of parent clocks for Muxes in CMU_HSI0 */
1354+
PNAME(mout_hsi0_noc_user_p) = { "oscclk", "dout_clkcmu_hsi0_noc" };
1355+
1356+
static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
1357+
MUX(CLK_MOUT_HSI0_NOC_USER, "mout_hsi0_noc_user",
1358+
mout_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 4, 1),
1359+
};
1360+
1361+
static const struct samsung_div_clock hsi0_div_clks[] __initconst = {
1362+
DIV(CLK_DOUT_HSI0_PCIE_APB, "dout_hsi0_pcie_apb",
1363+
"mout_hsi0_noc_user", CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
1364+
0, 4),
1365+
};
1366+
1367+
static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
1368+
.mux_clks = hsi0_mux_clks,
1369+
.nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
1370+
.div_clks = hsi0_div_clks,
1371+
.nr_div_clks = ARRAY_SIZE(hsi0_div_clks),
1372+
.nr_clk_ids = CLKS_NR_HSI0,
1373+
.clk_regs = hsi0_clk_regs,
1374+
.nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
1375+
.clk_name = "noc",
1376+
};
1377+
1378+
/* ---- CMU_HSI1 --------------------------------------------------------- */
1379+
1380+
/* Register Offset definitions for CMU_HSI1 (0x16400000) */
1381+
#define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x600
1382+
#define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER 0x610
1383+
#define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER 0x620
1384+
#define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD 0x1000
1385+
1386+
static const unsigned long hsi1_clk_regs[] __initconst = {
1387+
PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER,
1388+
PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER,
1389+
PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER,
1390+
CLK_CON_MUX_MUX_CLK_HSI1_USBDRD,
1391+
};
1392+
1393+
/* List of parent clocks for Muxes in CMU_HSI1 */
1394+
PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"};
1395+
PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };
1396+
PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" };
1397+
PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" };
1398+
1399+
static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
1400+
MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user",
1401+
mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 4, 1),
1402+
MUX(CLK_MOUT_HSI1_NOC_USER, "mout_hsi1_noc_user",
1403+
mout_hsi1_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 4, 1),
1404+
MUX(CLK_MOUT_HSI1_USBDRD_USER, "mout_hsi1_usbdrd_user",
1405+
mout_hsi1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 4, 1),
1406+
MUX(CLK_MOUT_HSI1_USBDRD, "mout_hsi1_usbdrd",
1407+
mout_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 4, 1),
1408+
};
1409+
1410+
static const struct samsung_cmu_info hsi1_cmu_info __initconst = {
1411+
.mux_clks = hsi1_mux_clks,
1412+
.nr_mux_clks = ARRAY_SIZE(hsi1_mux_clks),
1413+
.nr_clk_ids = CLKS_NR_HSI1,
1414+
.clk_regs = hsi1_clk_regs,
1415+
.nr_clk_regs = ARRAY_SIZE(hsi1_clk_regs),
1416+
.clk_name = "noc",
1417+
};
1418+
11421419
static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
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{
11441421
const struct samsung_cmu_info *info;
@@ -1154,6 +1431,18 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = {
11541431
{
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.compatible = "samsung,exynosautov920-cmu-peric0",
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.data = &peric0_cmu_info,
1434+
}, {
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.compatible = "samsung,exynosautov920-cmu-peric1",
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.data = &peric1_cmu_info,
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}, {
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.compatible = "samsung,exynosautov920-cmu-misc",
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.data = &misc_cmu_info,
1440+
}, {
1441+
.compatible = "samsung,exynosautov920-cmu-hsi0",
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.data = &hsi0_cmu_info,
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}, {
1444+
.compatible = "samsung,exynosautov920-cmu-hsi1",
1445+
.data = &hsi1_cmu_info,
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},
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{ }
11591448
};

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