@@ -1279,59 +1279,51 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
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{
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struct hns_roce_v2_priv * priv = hr_dev -> priv ;
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struct hns_roce_v2_cmq_ring * csq = & priv -> cmq .csq ;
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- struct hns_roce_cmq_desc * desc_to_use ;
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u32 timeout = 0 ;
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- int handle = 0 ;
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u16 desc_ret ;
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u32 tail ;
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int ret ;
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+ int i ;
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spin_lock_bh (& csq -> lock );
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tail = csq -> head ;
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- while (handle < num ) {
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- desc_to_use = & csq -> desc [csq -> head ];
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- * desc_to_use = desc [handle ];
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- dev_dbg (hr_dev -> dev , "set cmq desc:\n" );
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- csq -> head ++ ;
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+ for (i = 0 ; i < num ; i ++ ) {
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+ csq -> desc [csq -> head ++ ] = desc [i ];
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if (csq -> head == csq -> desc_num )
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csq -> head = 0 ;
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- handle ++ ;
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}
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/* Write to hardware */
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roce_write (hr_dev , ROCEE_TX_CMQ_HEAD_REG , csq -> head );
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- /*
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- * If the command is sync, wait for the firmware to write back,
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+ /* If the command is sync, wait for the firmware to write back,
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* if multi descriptors to be sent, use the first one to check
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*/
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if (le16_to_cpu (desc -> flag ) & HNS_ROCE_CMD_FLAG_NO_INTR ) {
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do {
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if (hns_roce_cmq_csq_done (hr_dev ))
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break ;
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udelay (1 );
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- timeout ++ ;
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- } while (timeout < priv -> cmq .tx_timeout );
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+ } while (++ timeout < priv -> cmq .tx_timeout );
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}
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if (hns_roce_cmq_csq_done (hr_dev )) {
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- handle = 0 ;
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- ret = 0 ;
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- while (handle < num ) {
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- /* get the result of hardware write back */
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- desc_to_use = & csq -> desc [tail ];
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- desc [handle ] = * desc_to_use ;
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- dev_dbg (hr_dev -> dev , "Get cmq desc:\n" );
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- desc_ret = le16_to_cpu (desc [handle ].retval );
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- if (unlikely (desc_ret != CMD_EXEC_SUCCESS ))
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- ret = - EIO ;
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-
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- tail ++ ;
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- handle ++ ;
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+ for (ret = 0 , i = 0 ; i < num ; i ++ ) {
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+ /* check the result of hardware write back */
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+ desc [i ] = csq -> desc [tail ++ ];
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if (tail == csq -> desc_num )
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tail = 0 ;
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+
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+ desc_ret = le16_to_cpu (desc [i ].retval );
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+ if (likely (desc_ret == CMD_EXEC_SUCCESS ))
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+ continue ;
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+
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+ dev_err_ratelimited (hr_dev -> dev ,
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+ "Cmdq IO error, opcode = %x, return = %x\n" ,
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+ desc -> opcode , desc_ret );
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+ ret = - EIO ;
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}
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} else {
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/* FW/HW reset or incorrect number of desc */
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