@@ -56,6 +56,24 @@ struct feature_id_reg {
56
56
};
57
57
58
58
static struct feature_id_reg feat_id_regs [] = {
59
+ {
60
+ ARM64_SYS_REG (3 , 0 , 2 , 0 , 3 ), /* TCR2_EL1 */
61
+ ARM64_SYS_REG (3 , 0 , 0 , 7 , 3 ), /* ID_AA64MMFR3_EL1 */
62
+ 0 ,
63
+ 1
64
+ },
65
+ {
66
+ ARM64_SYS_REG (3 , 0 , 10 , 2 , 2 ), /* PIRE0_EL1 */
67
+ ARM64_SYS_REG (3 , 0 , 0 , 7 , 3 ), /* ID_AA64MMFR3_EL1 */
68
+ 4 ,
69
+ 1
70
+ },
71
+ {
72
+ ARM64_SYS_REG (3 , 0 , 10 , 2 , 3 ), /* PIR_EL1 */
73
+ ARM64_SYS_REG (3 , 0 , 0 , 7 , 3 ), /* ID_AA64MMFR3_EL1 */
74
+ 4 ,
75
+ 1
76
+ }
59
77
};
60
78
61
79
struct vcpu_config {
@@ -873,12 +891,15 @@ static __u64 base_regs[] = {
873
891
ARM64_SYS_REG (3 , 0 , 2 , 0 , 0 ), /* TTBR0_EL1 */
874
892
ARM64_SYS_REG (3 , 0 , 2 , 0 , 1 ), /* TTBR1_EL1 */
875
893
ARM64_SYS_REG (3 , 0 , 2 , 0 , 2 ), /* TCR_EL1 */
894
+ ARM64_SYS_REG (3 , 0 , 2 , 0 , 3 ), /* TCR2_EL1 */
876
895
ARM64_SYS_REG (3 , 0 , 5 , 1 , 0 ), /* AFSR0_EL1 */
877
896
ARM64_SYS_REG (3 , 0 , 5 , 1 , 1 ), /* AFSR1_EL1 */
878
897
ARM64_SYS_REG (3 , 0 , 5 , 2 , 0 ), /* ESR_EL1 */
879
898
ARM64_SYS_REG (3 , 0 , 6 , 0 , 0 ), /* FAR_EL1 */
880
899
ARM64_SYS_REG (3 , 0 , 7 , 4 , 0 ), /* PAR_EL1 */
881
900
ARM64_SYS_REG (3 , 0 , 10 , 2 , 0 ), /* MAIR_EL1 */
901
+ ARM64_SYS_REG (3 , 0 , 10 , 2 , 2 ), /* PIRE0_EL1 */
902
+ ARM64_SYS_REG (3 , 0 , 10 , 2 , 3 ), /* PIR_EL1 */
882
903
ARM64_SYS_REG (3 , 0 , 10 , 3 , 0 ), /* AMAIR_EL1 */
883
904
ARM64_SYS_REG (3 , 0 , 12 , 0 , 0 ), /* VBAR_EL1 */
884
905
ARM64_SYS_REG (3 , 0 , 12 , 1 , 1 ), /* DISR_EL1 */
0 commit comments