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torvaldstorvalds
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "A couple fixes to the core framework logic that finds clk parents, a handful of samsung clk driver fixes for audio and display clks, and a small fix for the Stratix10 SoC driver that was checking the wrong register for validity" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: Fix potential NULL dereference in clk_fetch_parent_index() clk: Fix falling back to legacy parent string matching clk: socfpga: stratix10: fix rate caclulationg for cnt_clks clk: samsung: exynos542x: Move MSCL subsystem clocks to its sub-CMU clk: samsung: exynos5800: Move MAU subsystem clocks to MAU sub-CMU clk: samsung: Change signature of exynos5_subcmus_init() function
2 parents 287c55e + 24876f0 commit 5f97cbe

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6 files changed

+163
-75
lines changed

6 files changed

+163
-75
lines changed

‎drivers/clk/clk.c

Lines changed: 36 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -324,6 +324,25 @@ static struct clk_core *clk_core_lookup(const char *name)
324324
return NULL;
325325
}
326326

327+
#ifdef CONFIG_OF
328+
static int of_parse_clkspec(const struct device_node *np, int index,
329+
const char *name, struct of_phandle_args *out_args);
330+
static struct clk_hw *
331+
of_clk_get_hw_from_clkspec(struct of_phandle_args *clkspec);
332+
#else
333+
static inline int of_parse_clkspec(const struct device_node *np, int index,
334+
const char *name,
335+
struct of_phandle_args *out_args)
336+
{
337+
return -ENOENT;
338+
}
339+
static inline struct clk_hw *
340+
of_clk_get_hw_from_clkspec(struct of_phandle_args *clkspec)
341+
{
342+
return ERR_PTR(-ENOENT);
343+
}
344+
#endif
345+
327346
/**
328347
* clk_core_get - Find the clk_core parent of a clk
329348
* @core: clk to find parent of
@@ -355,8 +374,9 @@ static struct clk_core *clk_core_lookup(const char *name)
355374
* };
356375
*
357376
* Returns: -ENOENT when the provider can't be found or the clk doesn't
358-
* exist in the provider. -EINVAL when the name can't be found. NULL when the
359-
* provider knows about the clk but it isn't provided on this system.
377+
* exist in the provider or the name can't be found in the DT node or
378+
* in a clkdev lookup. NULL when the provider knows about the clk but it
379+
* isn't provided on this system.
360380
* A valid clk_core pointer when the clk can be found in the provider.
361381
*/
362382
static struct clk_core *clk_core_get(struct clk_core *core, u8 p_index)
@@ -367,17 +387,19 @@ static struct clk_core *clk_core_get(struct clk_core *core, u8 p_index)
367387
struct device *dev = core->dev;
368388
const char *dev_id = dev ? dev_name(dev) : NULL;
369389
struct device_node *np = core->of_node;
390+
struct of_phandle_args clkspec;
370391

371-
if (np && (name || index >= 0))
372-
hw = of_clk_get_hw(np, index, name);
373-
374-
/*
375-
* If the DT search above couldn't find the provider or the provider
376-
* didn't know about this clk, fallback to looking up via clkdev based
377-
* clk_lookups
378-
*/
379-
if (PTR_ERR(hw) == -ENOENT && name)
392+
if (np && (name || index >= 0) &&
393+
!of_parse_clkspec(np, index, name, &clkspec)) {
394+
hw = of_clk_get_hw_from_clkspec(&clkspec);
395+
of_node_put(clkspec.np);
396+
} else if (name) {
397+
/*
398+
* If the DT search above couldn't find the provider fallback to
399+
* looking up via clkdev based clk_lookups.
400+
*/
380401
hw = clk_find_hw(dev_id, name);
402+
}
381403

382404
if (IS_ERR(hw))
383405
return ERR_CAST(hw);
@@ -401,7 +423,7 @@ static void clk_core_fill_parent_index(struct clk_core *core, u8 index)
401423
parent = ERR_PTR(-EPROBE_DEFER);
402424
} else {
403425
parent = clk_core_get(core, index);
404-
if (IS_ERR(parent) && PTR_ERR(parent) == -ENOENT)
426+
if (IS_ERR(parent) && PTR_ERR(parent) == -ENOENT && entry->name)
405427
parent = clk_core_lookup(entry->name);
406428
}
407429

@@ -1632,7 +1654,8 @@ static int clk_fetch_parent_index(struct clk_core *core,
16321654
break;
16331655

16341656
/* Fallback to comparing globally unique names */
1635-
if (!strcmp(parent->name, core->parents[i].name))
1657+
if (core->parents[i].name &&
1658+
!strcmp(parent->name, core->parents[i].name))
16361659
break;
16371660
}
16381661

‎drivers/clk/samsung/clk-exynos5-subcmu.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
#include "clk-exynos5-subcmu.h"
1515

1616
static struct samsung_clk_provider *ctx;
17-
static const struct exynos5_subcmu_info *cmu;
17+
static const struct exynos5_subcmu_info **cmu;
1818
static int nr_cmus;
1919

2020
static void exynos5_subcmu_clk_save(void __iomem *base,
@@ -56,17 +56,17 @@ static void exynos5_subcmu_defer_gate(struct samsung_clk_provider *ctx,
5656
* when OF-core populates all device-tree nodes.
5757
*/
5858
void exynos5_subcmus_init(struct samsung_clk_provider *_ctx, int _nr_cmus,
59-
const struct exynos5_subcmu_info *_cmu)
59+
const struct exynos5_subcmu_info **_cmu)
6060
{
6161
ctx = _ctx;
6262
cmu = _cmu;
6363
nr_cmus = _nr_cmus;
6464

6565
for (; _nr_cmus--; _cmu++) {
66-
exynos5_subcmu_defer_gate(ctx, _cmu->gate_clks,
67-
_cmu->nr_gate_clks);
68-
exynos5_subcmu_clk_save(ctx->reg_base, _cmu->suspend_regs,
69-
_cmu->nr_suspend_regs);
66+
exynos5_subcmu_defer_gate(ctx, (*_cmu)->gate_clks,
67+
(*_cmu)->nr_gate_clks);
68+
exynos5_subcmu_clk_save(ctx->reg_base, (*_cmu)->suspend_regs,
69+
(*_cmu)->nr_suspend_regs);
7070
}
7171
}
7272

@@ -163,9 +163,9 @@ static int __init exynos5_clk_probe(struct platform_device *pdev)
163163
if (of_property_read_string(np, "label", &name) < 0)
164164
continue;
165165
for (i = 0; i < nr_cmus; i++)
166-
if (strcmp(cmu[i].pd_name, name) == 0)
166+
if (strcmp(cmu[i]->pd_name, name) == 0)
167167
exynos5_clk_register_subcmu(&pdev->dev,
168-
&cmu[i], np);
168+
cmu[i], np);
169169
}
170170
return 0;
171171
}

‎drivers/clk/samsung/clk-exynos5-subcmu.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,6 @@ struct exynos5_subcmu_info {
2121
};
2222

2323
void exynos5_subcmus_init(struct samsung_clk_provider *ctx, int nr_cmus,
24-
const struct exynos5_subcmu_info *cmu);
24+
const struct exynos5_subcmu_info **cmu);
2525

2626
#endif

‎drivers/clk/samsung/clk-exynos5250.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -681,6 +681,10 @@ static const struct exynos5_subcmu_info exynos5250_disp_subcmu = {
681681
.pd_name = "DISP1",
682682
};
683683

684+
static const struct exynos5_subcmu_info *exynos5250_subcmus[] = {
685+
&exynos5250_disp_subcmu,
686+
};
687+
684688
static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
685689
/* sorted in descending order */
686690
/* PLL_36XX_RATE(rate, m, p, s, k) */
@@ -843,7 +847,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
843847

844848
samsung_clk_sleep_init(reg_base, exynos5250_clk_regs,
845849
ARRAY_SIZE(exynos5250_clk_regs));
846-
exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu);
850+
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus),
851+
exynos5250_subcmus);
847852

848853
samsung_clk_of_add_provider(np, ctx);
849854

‎drivers/clk/samsung/clk-exynos5420.c

Lines changed: 111 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -534,8 +534,6 @@ static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
534534
GATE_BUS_TOP, 24, 0, 0),
535535
GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
536536
GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
537-
GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
538-
SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
539537
};
540538

541539
static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
@@ -577,8 +575,13 @@ static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
577575

578576
static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
579577
GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
578+
/* Maudio Block */
580579
GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
581580
SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
581+
GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
582+
GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
583+
GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
584+
GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
582585
};
583586

584587
static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
@@ -890,9 +893,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
890893
/* GSCL Block */
891894
DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
892895

893-
/* MSCL Block */
894-
DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
895-
896896
/* PSGEN */
897897
DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
898898
DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
@@ -1017,12 +1017,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
10171017
GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
10181018
GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
10191019

1020-
/* Maudio Block */
1021-
GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
1022-
GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1023-
GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
1024-
GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1025-
10261020
/* FSYS Block */
10271021
GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
10281022
GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
@@ -1162,17 +1156,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
11621156
GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
11631157
GATE_IP_GSCL1, 17, 0, 0),
11641158

1165-
/* MSCL Block */
1166-
GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1167-
GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1168-
GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1169-
GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1170-
GATE_IP_MSCL, 8, 0, 0),
1171-
GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1172-
GATE_IP_MSCL, 9, 0, 0),
1173-
GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1174-
GATE_IP_MSCL, 10, 0, 0),
1175-
11761159
/* ISP */
11771160
GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
11781161
GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
@@ -1281,32 +1264,103 @@ static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {
12811264
{ DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */
12821265
};
12831266

1284-
static const struct exynos5_subcmu_info exynos5x_subcmus[] = {
1285-
{
1286-
.div_clks = exynos5x_disp_div_clks,
1287-
.nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks),
1288-
.gate_clks = exynos5x_disp_gate_clks,
1289-
.nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks),
1290-
.suspend_regs = exynos5x_disp_suspend_regs,
1291-
.nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
1292-
.pd_name = "DISP",
1293-
}, {
1294-
.div_clks = exynos5x_gsc_div_clks,
1295-
.nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks),
1296-
.gate_clks = exynos5x_gsc_gate_clks,
1297-
.nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks),
1298-
.suspend_regs = exynos5x_gsc_suspend_regs,
1299-
.nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
1300-
.pd_name = "GSC",
1301-
}, {
1302-
.div_clks = exynos5x_mfc_div_clks,
1303-
.nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
1304-
.gate_clks = exynos5x_mfc_gate_clks,
1305-
.nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks),
1306-
.suspend_regs = exynos5x_mfc_suspend_regs,
1307-
.nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
1308-
.pd_name = "MFC",
1309-
},
1267+
static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = {
1268+
/* MSCL Block */
1269+
GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1270+
GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1271+
GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1272+
GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1273+
GATE_IP_MSCL, 8, 0, 0),
1274+
GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1275+
GATE_IP_MSCL, 9, 0, 0),
1276+
GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1277+
GATE_IP_MSCL, 10, 0, 0),
1278+
};
1279+
1280+
static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = {
1281+
DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
1282+
};
1283+
1284+
static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = {
1285+
{ GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */
1286+
{ SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */
1287+
{ DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */
1288+
};
1289+
1290+
static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = {
1291+
GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
1292+
SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
1293+
GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
1294+
GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1295+
GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
1296+
GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1297+
};
1298+
1299+
static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = {
1300+
{ SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */
1301+
};
1302+
1303+
static const struct exynos5_subcmu_info exynos5x_disp_subcmu = {
1304+
.div_clks = exynos5x_disp_div_clks,
1305+
.nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks),
1306+
.gate_clks = exynos5x_disp_gate_clks,
1307+
.nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks),
1308+
.suspend_regs = exynos5x_disp_suspend_regs,
1309+
.nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
1310+
.pd_name = "DISP",
1311+
};
1312+
1313+
static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {
1314+
.div_clks = exynos5x_gsc_div_clks,
1315+
.nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks),
1316+
.gate_clks = exynos5x_gsc_gate_clks,
1317+
.nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks),
1318+
.suspend_regs = exynos5x_gsc_suspend_regs,
1319+
.nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
1320+
.pd_name = "GSC",
1321+
};
1322+
1323+
static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
1324+
.div_clks = exynos5x_mfc_div_clks,
1325+
.nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
1326+
.gate_clks = exynos5x_mfc_gate_clks,
1327+
.nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks),
1328+
.suspend_regs = exynos5x_mfc_suspend_regs,
1329+
.nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
1330+
.pd_name = "MFC",
1331+
};
1332+
1333+
static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = {
1334+
.div_clks = exynos5x_mscl_div_clks,
1335+
.nr_div_clks = ARRAY_SIZE(exynos5x_mscl_div_clks),
1336+
.gate_clks = exynos5x_mscl_gate_clks,
1337+
.nr_gate_clks = ARRAY_SIZE(exynos5x_mscl_gate_clks),
1338+
.suspend_regs = exynos5x_mscl_suspend_regs,
1339+
.nr_suspend_regs = ARRAY_SIZE(exynos5x_mscl_suspend_regs),
1340+
.pd_name = "MSC",
1341+
};
1342+
1343+
static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
1344+
.gate_clks = exynos5800_mau_gate_clks,
1345+
.nr_gate_clks = ARRAY_SIZE(exynos5800_mau_gate_clks),
1346+
.suspend_regs = exynos5800_mau_suspend_regs,
1347+
.nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs),
1348+
.pd_name = "MAU",
1349+
};
1350+
1351+
static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
1352+
&exynos5x_disp_subcmu,
1353+
&exynos5x_gsc_subcmu,
1354+
&exynos5x_mfc_subcmu,
1355+
&exynos5x_mscl_subcmu,
1356+
};
1357+
1358+
static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
1359+
&exynos5x_disp_subcmu,
1360+
&exynos5x_gsc_subcmu,
1361+
&exynos5x_mfc_subcmu,
1362+
&exynos5x_mscl_subcmu,
1363+
&exynos5800_mau_subcmu,
13101364
};
13111365

13121366
static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
@@ -1539,11 +1593,17 @@ static void __init exynos5x_clk_init(struct device_node *np,
15391593
samsung_clk_extended_sleep_init(reg_base,
15401594
exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
15411595
exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
1542-
if (soc == EXYNOS5800)
1596+
1597+
if (soc == EXYNOS5800) {
15431598
samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
15441599
ARRAY_SIZE(exynos5800_clk_regs));
1545-
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
1546-
exynos5x_subcmus);
1600+
1601+
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus),
1602+
exynos5800_subcmus);
1603+
} else {
1604+
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
1605+
exynos5x_subcmus);
1606+
}
15471607

15481608
samsung_clk_of_add_provider(np, ctx);
15491609
}

‎drivers/clk/socfpga/clk-periph-s10.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
3838
if (socfpgaclk->fixed_div) {
3939
div = socfpgaclk->fixed_div;
4040
} else {
41-
if (!socfpgaclk->bypass_reg)
41+
if (socfpgaclk->hw.reg)
4242
div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
4343
}
4444

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