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Merge tag 'clk-v5.5-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki: - Addition of rate table for the VPLL and GPU related clock tree definition update to allow the GPU driver for setting the GPU's clock without requiring detailed knowledge of clock topology on each exynos542x SoC - Fix for potential CPU performance degradation after system suspend/resume cycle on exynos542x SoCs * tag 'clk-v5.5-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume clk: samsung: exynos5420: Add VPLL rate table clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU clk: samsung: exynos5433: Fix error paths
2 parents 54ecb8f + 45f10da commit 6063244

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‎drivers/clk/samsung/clk-exynos5420.c

Lines changed: 50 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -165,12 +165,20 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
165165
GATE_BUS_CPU,
166166
GATE_SCLK_CPU,
167167
CLKOUT_CMU_CPU,
168+
APLL_CON0,
169+
KPLL_CON0,
170+
CPLL_CON0,
171+
DPLL_CON0,
168172
EPLL_CON0,
169173
EPLL_CON1,
170174
EPLL_CON2,
171175
RPLL_CON0,
172176
RPLL_CON1,
173177
RPLL_CON2,
178+
IPLL_CON0,
179+
SPLL_CON0,
180+
VPLL_CON0,
181+
MPLL_CON0,
174182
SRC_TOP0,
175183
SRC_TOP1,
176184
SRC_TOP2,
@@ -605,7 +613,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
605613
MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
606614
MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
607615

608-
MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
616+
MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1,
617+
CLK_SET_RATE_PARENT, 0),
609618

610619
MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
611620
SRC_TOP3, 0, 1),
@@ -647,8 +656,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
647656
SRC_TOP5, 8, 1),
648657
MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
649658
SRC_TOP5, 12, 1),
650-
MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
651-
SRC_TOP5, 16, 1),
659+
MUX_F(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
660+
SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0),
652661
MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
653662
SRC_TOP5, 20, 1),
654663
MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
@@ -657,7 +666,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
657666
mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
658667

659668
MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
660-
MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
669+
MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1,
670+
CLK_SET_RATE_PARENT, 0),
661671
MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
662672
MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
663673
MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
@@ -701,7 +711,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
701711
SRC_TOP12, 8, 1),
702712
MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
703713
SRC_TOP12, 12, 1),
704-
MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
714+
MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1,
715+
CLK_SET_RATE_PARENT, 0),
705716
MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
706717
SRC_TOP12, 20, 1),
707718
MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
@@ -798,8 +809,8 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
798809
DIV_TOP2, 8, 3),
799810
DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
800811
DIV_TOP2, 12, 3),
801-
DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
802-
16, 3),
812+
DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
813+
16, 3, CLK_SET_RATE_PARENT, 0),
803814
DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
804815
DIV_TOP2, 20, 3),
805816
DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
@@ -1172,8 +1183,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
11721183
GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
11731184
GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
11741185

1175-
GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1176-
11771186
/* CDREX */
11781187
GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
11791188
GATE_BUS_CDREX0, 0, 0, 0),
@@ -1248,6 +1257,16 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
12481257
{ DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
12491258
};
12501259

1260+
static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
1261+
GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
1262+
CLK_SET_RATE_PARENT, 0),
1263+
};
1264+
1265+
static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = {
1266+
{ GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */
1267+
{ SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */
1268+
};
1269+
12511270
static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
12521271
DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
12531272
};
@@ -1320,6 +1339,14 @@ static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {
13201339
.pd_name = "GSC",
13211340
};
13221341

1342+
static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = {
1343+
.gate_clks = exynos5x_g3d_gate_clks,
1344+
.nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks),
1345+
.suspend_regs = exynos5x_g3d_suspend_regs,
1346+
.nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs),
1347+
.pd_name = "G3D",
1348+
};
1349+
13231350
static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
13241351
.div_clks = exynos5x_mfc_div_clks,
13251352
.nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
@@ -1351,13 +1378,15 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
13511378
static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
13521379
&exynos5x_disp_subcmu,
13531380
&exynos5x_gsc_subcmu,
1381+
&exynos5x_g3d_subcmu,
13541382
&exynos5x_mfc_subcmu,
13551383
&exynos5x_mscl_subcmu,
13561384
};
13571385

13581386
static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
13591387
&exynos5x_disp_subcmu,
13601388
&exynos5x_gsc_subcmu,
1389+
&exynos5x_g3d_subcmu,
13611390
&exynos5x_mfc_subcmu,
13621391
&exynos5x_mscl_subcmu,
13631392
&exynos5800_mau_subcmu,
@@ -1414,6 +1443,17 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
14141443
PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719),
14151444
};
14161445

1446+
static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = {
1447+
PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2),
1448+
PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2),
1449+
PLL_35XX_RATE(24 * MHZ, 480000000U, 160, 2, 2),
1450+
PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2),
1451+
PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2),
1452+
PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3),
1453+
PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3),
1454+
PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4),
1455+
};
1456+
14171457
static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
14181458
[apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
14191459
APLL_CON0, NULL),
@@ -1538,6 +1578,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
15381578
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
15391579
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
15401580
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1581+
exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
15411582
}
15421583

15431584
if (soc == EXYNOS5420)

‎drivers/clk/samsung/clk-exynos5433.c

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#include <linux/of_device.h>
1414
#include <linux/platform_device.h>
1515
#include <linux/pm_runtime.h>
16+
#include <linux/slab.h>
1617

1718
#include <dt-bindings/clock/exynos5433.h>
1819

@@ -5584,6 +5585,8 @@ static int __init exynos5433_cmu_probe(struct platform_device *pdev)
55845585

55855586
data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs,
55865587
info->nr_clk_regs);
5588+
if (!data->clk_save)
5589+
return -ENOMEM;
55875590
data->nr_clk_save = info->nr_clk_regs;
55885591
data->clk_suspend = info->suspend_regs;
55895592
data->nr_clk_suspend = info->nr_suspend_regs;
@@ -5592,12 +5595,19 @@ static int __init exynos5433_cmu_probe(struct platform_device *pdev)
55925595
if (data->nr_pclks > 0) {
55935596
data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
55945597
data->nr_pclks, GFP_KERNEL);
5595-
5598+
if (!data->pclks) {
5599+
kfree(data->clk_save);
5600+
return -ENOMEM;
5601+
}
55965602
for (i = 0; i < data->nr_pclks; i++) {
55975603
struct clk *clk = of_clk_get(dev->of_node, i);
55985604

5599-
if (IS_ERR(clk))
5605+
if (IS_ERR(clk)) {
5606+
kfree(data->clk_save);
5607+
while (--i >= 0)
5608+
clk_put(data->pclks[i]);
56005609
return PTR_ERR(clk);
5610+
}
56015611
data->pclks[i] = clk;
56025612
}
56035613
}

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