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Ben Skeggs
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drm/nouveau/fence: use NVIDIA's headers for emit()
Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
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6 files changed

+100
-21
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6 files changed

+100
-21
lines changed

‎drivers/gpu/drm/nouveau/include/nvhw/class/cl006e.h

Lines changed: 30 additions & 0 deletions
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@@ -0,0 +1,30 @@
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/*******************************************************************************
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Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
9+
Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#ifndef _cl006e_h_
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#define _cl006e_h_
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/* fields and values */
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#define NV06E_SET_OBJECT (0x00000000)
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#define NV06E_REFERENCE (0x00000048)
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#define NV06E_SET_REFERENCE (0x00000050)
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#endif /* _cl006e_h_ */

‎drivers/gpu/drm/nouveau/include/nvhw/class/cl826f.h

Lines changed: 39 additions & 0 deletions
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@@ -0,0 +1,39 @@
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/*******************************************************************************
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Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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Permission is hereby granted, free of charge, to any person obtaining a
5+
copy of this software and associated documentation files (the "Software"),
6+
to deal in the Software without restriction, including without limitation
7+
the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+
and/or sell copies of the Software, and to permit persons to whom the
9+
Software is furnished to do so, subject to the following conditions:
10+
11+
The above copyright notice and this permission notice shall be included in
12+
all copies or substantial portions of the Software.
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14+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18+
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#ifndef _cl826f_h_
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#define _cl826f_h_
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#define NV826F_SEMAPHOREA (0x00000010)
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#define NV826F_SEMAPHOREA_OFFSET_UPPER 7:0
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#define NV826F_SEMAPHOREB (0x00000014)
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#define NV826F_SEMAPHOREB_OFFSET_LOWER 31:00
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#define NV826F_SEMAPHOREC (0x00000018)
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#define NV826F_SEMAPHOREC_PAYLOAD 31:0
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#define NV826F_SEMAPHORED (0x0000001C)
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#define NV826F_SEMAPHORED_OPERATION 2:0
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#define NV826F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
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#define NV826F_SEMAPHORED_OPERATION_RELEASE 0x00000002
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#define NV826F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
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#define NV826F_NON_STALLED_INTERRUPT (0x00000020)
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#define NV826F_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
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#endif /* _cl826f_h_ */

‎drivers/gpu/drm/nouveau/nouveau_dma.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,6 @@ WIND_RING(struct nouveau_channel *chan)
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}
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106106
/* FIFO methods */
107-
#define NV01_SUBCHAN_OBJECT 0x00000000
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#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
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#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
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#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
@@ -113,14 +112,10 @@ WIND_RING(struct nouveau_channel *chan)
113112
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
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#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
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#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
116-
#define NV84_SUBCHAN_UEVENT 0x00000020
117-
#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
118-
#define NV10_SUBCHAN_REF_CNT 0x00000050
119115
#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
120116
#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
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#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
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#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
123-
#define NV40_SUBCHAN_YIELD 0x00000080
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125120
/* NV_SW object class */
126121
#define NV_SW_DMA_VBLSEM 0x0000018c

‎drivers/gpu/drm/nouveau/nv10_fence.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,13 +27,15 @@
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#include <nvif/push006c.h>
2929

30+
#include <nvhw/class/cl006e.h>
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3032
int
3133
nv10_fence_emit(struct nouveau_fence *fence)
3234
{
3335
struct nvif_push *push = fence->channel->chan.push;
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int ret = PUSH_WAIT(push, 2);
3537
if (ret == 0) {
36-
PUSH_NVSQ(push, NV06E, NV10_SUBCHAN_REF_CNT, fence->base.seqno);
38+
PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno);
3739
PUSH_KICK(push);
3840
}
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return ret;

‎drivers/gpu/drm/nouveau/nv84_fence.c

Lines changed: 14 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -30,20 +30,26 @@
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3131
#include <nvif/push206e.h>
3232

33+
#include <nvhw/class/cl826f.h>
34+
3335
static int
3436
nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
3537
{
3638
struct nvif_push *push = chan->chan.push;
3739
int ret = PUSH_WAIT(push, 8);
3840
if (ret == 0) {
39-
PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle);
40-
PUSH_NVSQ(push, NV826F,
41-
NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
42-
NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
43-
NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
44-
NV84_SUBCHAN_SEMAPHORE_TRIGGER,
45-
NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG,
46-
NV84_SUBCHAN_UEVENT, 0x00000000);
41+
PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
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43+
PUSH_MTHD(push, NV826F, SEMAPHOREA,
44+
NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
45+
46+
SEMAPHOREB, lower_32_bits(virtual),
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SEMAPHOREC, sequence,
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SEMAPHORED,
50+
NVDEF(NV826F, SEMAPHORED, OPERATION, RELEASE),
51+
52+
NON_STALLED_INTERRUPT, 0);
4753
PUSH_KICK(push);
4854
}
4955
return ret;

‎drivers/gpu/drm/nouveau/nvc0_fence.c

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -29,19 +29,26 @@
2929

3030
#include <nvif/push906f.h>
3131

32+
#include <nvhw/class/cl906f.h>
33+
3234
static int
3335
nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
3436
{
3537
struct nvif_push *push = chan->chan.push;
3638
int ret = PUSH_WAIT(push, 6);
3739
if (ret == 0) {
38-
PUSH_NVSQ(push, NV906F,
39-
NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
40-
NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
41-
NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
42-
NV84_SUBCHAN_SEMAPHORE_TRIGGER,
43-
NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG,
44-
NV84_SUBCHAN_UEVENT, 0x00000000);
40+
PUSH_MTHD(push, NV906F, SEMAPHOREA,
41+
NVVAL(NV906F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
42+
43+
SEMAPHOREB, lower_32_bits(virtual),
44+
SEMAPHOREC, sequence,
45+
46+
SEMAPHORED,
47+
NVDEF(NV906F, SEMAPHORED, OPERATION, RELEASE) |
48+
NVDEF(NV906F, SEMAPHORED, RELEASE_WFI, EN) |
49+
NVDEF(NV906F, SEMAPHORED, RELEASE_SIZE, 16BYTE),
50+
51+
NON_STALL_INTERRUPT, 0);
4552
PUSH_KICK(push);
4653
}
4754
return ret;

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