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Merge branch 'for-5.8/dt-bindings' into for-5.8/media
2 parents 8f3d9f3 + 4e79691 commit 612c341

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‎Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt

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Binding for NVIDIA Tegra20 CPUFreq
2+
==================================
3+
4+
Required properties:
5+
- clocks: Must contain an entry for the CPU clock.
6+
See ../clocks/clock-bindings.txt for details.
7+
- operating-points-v2: See ../bindings/opp/opp.txt for details.
8+
- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details.
9+
10+
For each opp entry in 'operating-points-v2' table:
11+
- opp-supported-hw: Two bitfields indicating:
12+
On Tegra20:
13+
1. CPU process ID mask
14+
2. SoC speedo ID mask
15+
16+
On Tegra30:
17+
1. CPU process ID mask
18+
2. CPU speedo ID mask
19+
20+
A bitwise AND is performed against these values and if any bit
21+
matches, the OPP gets enabled.
22+
23+
- opp-microvolt: CPU voltage triplet.
24+
25+
Optional properties:
26+
- cpu-supply: Phandle to the CPU power supply.
27+
28+
Example:
29+
regulators {
30+
cpu_reg: regulator0 {
31+
regulator-name = "vdd_cpu";
32+
};
33+
};
34+
35+
cpu0_opp_table: opp_table0 {
36+
compatible = "operating-points-v2";
37+
38+
opp@456000000 {
39+
clock-latency-ns = <125000>;
40+
opp-microvolt = <825000 825000 1125000>;
41+
opp-supported-hw = <0x03 0x0001>;
42+
opp-hz = /bits/ 64 <456000000>;
43+
};
44+
45+
...
46+
};
47+
48+
cpus {
49+
cpu@0 {
50+
compatible = "arm,cortex-a9";
51+
clocks = <&tegra_car TEGRA20_CLK_CCLK>;
52+
operating-points-v2 = <&cpu0_opp_table>;
53+
cpu-supply = <&cpu_reg>;
54+
#cooling-cells = <2>;
55+
};
56+
};

‎Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt

Lines changed: 60 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -40,14 +40,30 @@ of the following host1x client modules:
4040

4141
Required properties:
4242
- compatible: "nvidia,tegra<chip>-vi"
43-
- reg: Physical base address and length of the controller's registers.
43+
- reg: Physical base address and length of the controller registers.
4444
- interrupts: The interrupt outputs from the controller.
45-
- clocks: Must contain one entry, for the module clock.
45+
- clocks: clocks: Must contain one entry, for the module clock.
4646
See ../clocks/clock-bindings.txt for details.
47-
- resets: Must contain an entry for each entry in reset-names.
48-
See ../reset/reset.txt for details.
49-
- reset-names: Must include the following entries:
50-
- vi
47+
- Tegra20/Tegra30/Tegra114/Tegra124:
48+
- resets: Must contain an entry for each entry in reset-names.
49+
See ../reset/reset.txt for details.
50+
- reset-names: Must include the following entries:
51+
- vi
52+
- Tegra210:
53+
- power-domains: Must include venc powergate node as vi is in VE partition.
54+
- Tegra210 has CSI part of VI sharing same host interface and register space.
55+
So, VI device node should have CSI child node.
56+
57+
- csi: mipi csi interface to vi
58+
59+
Required properties:
60+
- compatible: "nvidia,tegra210-csi"
61+
- reg: Physical base address offset to parent and length of the controller
62+
registers.
63+
- clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
64+
See ../clocks/clock-bindings.txt for details.
65+
- power-domains: Must include sor powergate node as csicil is in
66+
SOR partition.
5167

5268
- epp: encoder pre-processor
5369

@@ -309,13 +325,44 @@ Example:
309325
reset-names = "mpe";
310326
};
311327

312-
vi {
313-
compatible = "nvidia,tegra20-vi";
314-
reg = <0x54080000 0x00040000>;
315-
interrupts = <0 69 0x04>;
316-
clocks = <&tegra_car TEGRA20_CLK_VI>;
317-
resets = <&tegra_car 100>;
318-
reset-names = "vi";
328+
vi@54080000 {
329+
compatible = "nvidia,tegra210-vi";
330+
reg = <0x0 0x54080000 0x0 0x700>;
331+
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
332+
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
333+
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
334+
335+
clocks = <&tegra_car TEGRA210_CLK_VI>;
336+
power-domains = <&pd_venc>;
337+
338+
#address-cells = <1>;
339+
#size-cells = <1>;
340+
341+
ranges = <0x0 0x0 0x54080000 0x2000>;
342+
343+
csi@838 {
344+
compatible = "nvidia,tegra210-csi";
345+
reg = <0x838 0x1300>;
346+
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
347+
<&tegra_car TEGRA210_CLK_CILCD>,
348+
<&tegra_car TEGRA210_CLK_CILE>,
349+
<&tegra_car TEGRA210_CLK_CSI_TPG>;
350+
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
351+
<&tegra_car TEGRA210_CLK_PLL_P>,
352+
<&tegra_car TEGRA210_CLK_PLL_P>;
353+
assigned-clock-rates = <102000000>,
354+
<102000000>,
355+
<102000000>,
356+
<972000000>;
357+
358+
clocks = <&tegra_car TEGRA210_CLK_CSI>,
359+
<&tegra_car TEGRA210_CLK_CILAB>,
360+
<&tegra_car TEGRA210_CLK_CILCD>,
361+
<&tegra_car TEGRA210_CLK_CILE>,
362+
<&tegra_car TEGRA210_CLK_CSI_TPG>;
363+
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
364+
power-domains = <&pd_sor>;
365+
};
319366
};
320367

321368
epp {

‎Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt

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@@ -35,6 +35,12 @@ Required properties:
3535
Due to above changes, Tegra114 I2C driver makes incompatible with
3636
previous hardware driver. Hence, tegra114 I2C controller is compatible
3737
with "nvidia,tegra114-i2c".
38+
nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is part of the
39+
host1x domain and typically used for camera use-cases. This VI I2C
40+
controller is mostly compatible with the programming model of the
41+
regular I2C controllers with a few exceptions. The I2C registers start
42+
at an offset of 0xc00 (instead of 0), registers are 16 bytes apart
43+
(rather than 4) and the controller does not support slave mode.
3844
- reg: Should contain I2C controller registers physical address and length.
3945
- interrupts: Should contain I2C controller interrupts.
4046
- address-cells: Address cells for I2C device address.

‎Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: NVIDIA Tegra210 SoC External Memory Controller
8+
9+
maintainers:
10+
- Thierry Reding <[email protected]>
11+
- Jon Hunter <[email protected]>
12+
13+
description: |
14+
The EMC interfaces with the off-chip SDRAM to service the request stream
15+
sent from the memory controller.
16+
17+
properties:
18+
compatible:
19+
const: nvidia,tegra210-emc
20+
21+
reg:
22+
maxItems: 3
23+
24+
clocks:
25+
items:
26+
- description: external memory clock
27+
28+
clock-names:
29+
items:
30+
- const: emc
31+
32+
interrupts:
33+
items:
34+
- description: EMC general interrupt
35+
36+
memory-region:
37+
$ref: /schemas/types.yaml#/definitions/phandle
38+
description:
39+
phandle to a reserved memory region describing the table of EMC
40+
frequencies trained by the firmware
41+
42+
nvidia,memory-controller:
43+
$ref: /schemas/types.yaml#/definitions/phandle
44+
description:
45+
phandle of the memory controller node
46+
47+
required:
48+
- compatible
49+
- reg
50+
- clocks
51+
- clock-names
52+
- nvidia,memory-controller
53+
54+
additionalProperties: false
55+
56+
examples:
57+
- |
58+
#include <dt-bindings/clock/tegra210-car.h>
59+
#include <dt-bindings/interrupt-controller/arm-gic.h>
60+
61+
reserved-memory {
62+
#address-cells = <1>;
63+
#size-cells = <1>;
64+
ranges;
65+
66+
emc_table: emc-table@83400000 {
67+
compatible = "nvidia,tegra210-emc-table";
68+
reg = <0x83400000 0x10000>;
69+
};
70+
};
71+
72+
external-memory-controller@7001b000 {
73+
compatible = "nvidia,tegra210-emc";
74+
reg = <0x7001b000 0x1000>,
75+
<0x7001e000 0x1000>,
76+
<0x7001f000 0x1000>;
77+
clocks = <&tegra_car TEGRA210_CLK_EMC>;
78+
clock-names = "emc";
79+
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
80+
memory-region = <&emc_table>;
81+
nvidia,memory-controller = <&mc>;
82+
};

‎include/dt-bindings/clock/tegra114-car.h

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@@ -272,10 +272,10 @@
272272
#define TEGRA114_CLK_AUDIO3 242
273273
#define TEGRA114_CLK_AUDIO4 243
274274
#define TEGRA114_CLK_SPDIF 244
275-
#define TEGRA114_CLK_CLK_OUT_1 245
276-
#define TEGRA114_CLK_CLK_OUT_2 246
277-
#define TEGRA114_CLK_CLK_OUT_3 247
278-
#define TEGRA114_CLK_BLINK 248
275+
/* 245 */
276+
/* 246 */
277+
/* 247 */
278+
/* 248 */
279279
#define TEGRA114_CLK_OSC 249
280280
/* 250 */
281281
/* 251 */
@@ -335,9 +335,9 @@
335335
#define TEGRA114_CLK_AUDIO3_MUX 303
336336
#define TEGRA114_CLK_AUDIO4_MUX 304
337337
#define TEGRA114_CLK_SPDIF_MUX 305
338-
#define TEGRA114_CLK_CLK_OUT_1_MUX 306
339-
#define TEGRA114_CLK_CLK_OUT_2_MUX 307
340-
#define TEGRA114_CLK_CLK_OUT_3_MUX 308
338+
/* 306 */
339+
/* 307 */
340+
/* 308 */
341341
#define TEGRA114_CLK_DSIA_MUX 309
342342
#define TEGRA114_CLK_DSIB_MUX 310
343343
#define TEGRA114_CLK_XUSB_SS_DIV2 311

‎include/dt-bindings/clock/tegra124-car-common.h

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@@ -271,10 +271,10 @@
271271
#define TEGRA124_CLK_AUDIO3 242
272272
#define TEGRA124_CLK_AUDIO4 243
273273
#define TEGRA124_CLK_SPDIF 244
274-
#define TEGRA124_CLK_CLK_OUT_1 245
275-
#define TEGRA124_CLK_CLK_OUT_2 246
276-
#define TEGRA124_CLK_CLK_OUT_3 247
277-
#define TEGRA124_CLK_BLINK 248
274+
/* 245 */
275+
/* 246 */
276+
/* 247 */
277+
/* 248 */
278278
#define TEGRA124_CLK_OSC 249
279279
/* 250 */
280280
/* 251 */
@@ -334,9 +334,9 @@
334334
#define TEGRA124_CLK_AUDIO3_MUX 303
335335
#define TEGRA124_CLK_AUDIO4_MUX 304
336336
#define TEGRA124_CLK_SPDIF_MUX 305
337-
#define TEGRA124_CLK_CLK_OUT_1_MUX 306
338-
#define TEGRA124_CLK_CLK_OUT_2_MUX 307
339-
#define TEGRA124_CLK_CLK_OUT_3_MUX 308
337+
/* 306 */
338+
/* 307 */
339+
/* 308 */
340340
/* 309 */
341341
/* 310 */
342342
#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */

‎include/dt-bindings/clock/tegra20-car.h

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@@ -131,7 +131,7 @@
131131
#define TEGRA20_CLK_CCLK 108
132132
#define TEGRA20_CLK_HCLK 109
133133
#define TEGRA20_CLK_PCLK 110
134-
#define TEGRA20_CLK_BLINK 111
134+
/* 111 */
135135
#define TEGRA20_CLK_PLL_A 112
136136
#define TEGRA20_CLK_PLL_A_OUT0 113
137137
#define TEGRA20_CLK_PLL_C 114

‎include/dt-bindings/clock/tegra210-car.h

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -306,10 +306,10 @@
306306
#define TEGRA210_CLK_AUDIO3 274
307307
#define TEGRA210_CLK_AUDIO4 275
308308
#define TEGRA210_CLK_SPDIF 276
309-
#define TEGRA210_CLK_CLK_OUT_1 277
310-
#define TEGRA210_CLK_CLK_OUT_2 278
311-
#define TEGRA210_CLK_CLK_OUT_3 279
312-
#define TEGRA210_CLK_BLINK 280
309+
/* 277 */
310+
/* 278 */
311+
/* 279 */
312+
/* 280 */
313313
#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
314314
#define TEGRA210_CLK_SOR0_OUT 281
315315
#define TEGRA210_CLK_SOR1_OUT 282
@@ -358,7 +358,7 @@
358358
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
359359
/* 325 */
360360
#define TEGRA210_CLK_OSC 326
361-
/* 327 */
361+
#define TEGRA210_CLK_CSI_TPG 327
362362
/* 328 */
363363
/* 329 */
364364
/* 330 */
@@ -388,9 +388,9 @@
388388
#define TEGRA210_CLK_AUDIO3_MUX 353
389389
#define TEGRA210_CLK_AUDIO4_MUX 354
390390
#define TEGRA210_CLK_SPDIF_MUX 355
391-
#define TEGRA210_CLK_CLK_OUT_1_MUX 356
392-
#define TEGRA210_CLK_CLK_OUT_2_MUX 357
393-
#define TEGRA210_CLK_CLK_OUT_3_MUX 358
391+
/* 356 */
392+
/* 357 */
393+
/* 358 */
394394
#define TEGRA210_CLK_DSIA_MUX 359
395395
#define TEGRA210_CLK_DSIB_MUX 360
396396
/* 361 */

‎include/dt-bindings/clock/tegra30-car.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -232,11 +232,11 @@
232232
#define TEGRA30_CLK_AUDIO3 204
233233
#define TEGRA30_CLK_AUDIO4 205
234234
#define TEGRA30_CLK_SPDIF 206
235-
#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
236-
#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
237-
#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
235+
/* 207 */
236+
/* 208 */
237+
/* 209 */
238238
#define TEGRA30_CLK_SCLK 210
239-
#define TEGRA30_CLK_BLINK 211
239+
/* 211 */
240240
#define TEGRA30_CLK_CCLK_G 212
241241
#define TEGRA30_CLK_CCLK_LP 213
242242
#define TEGRA30_CLK_TWD 214
@@ -262,9 +262,9 @@
262262
/* 297 */
263263
/* 298 */
264264
/* 299 */
265-
#define TEGRA30_CLK_CLK_OUT_1_MUX 300
266-
#define TEGRA30_CLK_CLK_OUT_2_MUX 301
267-
#define TEGRA30_CLK_CLK_OUT_3_MUX 302
265+
/* 300 */
266+
/* 301 */
267+
/* 302 */
268268
#define TEGRA30_CLK_AUDIO0_MUX 303
269269
#define TEGRA30_CLK_AUDIO1_MUX 304
270270
#define TEGRA30_CLK_AUDIO2_MUX 305

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