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Merge branch 'for-next/sysregs' into for-next/core
* for-next/sysregs: (28 commits) arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generation arm64/sysreg: Convert LORID_EL1 to automatic generation arm64/sysreg: Convert LORC_EL1 to automatic generation arm64/sysreg: Convert LORN_EL1 to automatic generation arm64/sysreg: Convert LOREA_EL1 to automatic generation arm64/sysreg: Convert LORSA_EL1 to automatic generation arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation arm64/sysreg: Convert GMID to automatic generation arm64/sysreg: Convert DCZID_EL0 to automatic generation arm64/sysreg: Convert CTR_EL0 to automatic generation arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition names arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names arm64/sysreg: Remove defines for RPRES enumeration arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums arm64/sysreg: Standardise naming for WFxT defines arm64/sysreg: Make BHB clear feature defines match the architecture arm64/sysreg: Align pointer auth enumeration defines with architecture ...
2 parents cb20311 + 3bbeca9 commit 618ff55

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17 files changed

+457
-315
lines changed

17 files changed

+457
-315
lines changed

‎arch/arm64/include/asm/asm_pointer_auth.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -59,9 +59,9 @@ alternative_else_nop_endif
5959

6060
.macro __ptrauth_keys_init_cpu tsk, tmp1, tmp2, tmp3
6161
mrs \tmp1, id_aa64isar1_el1
62-
ubfx \tmp1, \tmp1, #ID_AA64ISAR1_APA_SHIFT, #8
62+
ubfx \tmp1, \tmp1, #ID_AA64ISAR1_EL1_APA_SHIFT, #8
6363
mrs_s \tmp2, SYS_ID_AA64ISAR2_EL1
64-
ubfx \tmp2, \tmp2, #ID_AA64ISAR2_APA3_SHIFT, #4
64+
ubfx \tmp2, \tmp2, #ID_AA64ISAR2_EL1_APA3_SHIFT, #4
6565
orr \tmp1, \tmp1, \tmp2
6666
cbz \tmp1, .Lno_addr_auth\@
6767
mov_q \tmp1, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | \

‎arch/arm64/include/asm/cache.h

Lines changed: 13 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -5,34 +5,9 @@
55
#ifndef __ASM_CACHE_H
66
#define __ASM_CACHE_H
77

8-
#include <asm/cputype.h>
9-
#include <asm/mte-def.h>
10-
11-
#define CTR_L1IP_SHIFT 14
12-
#define CTR_L1IP_MASK 3
13-
#define CTR_DMINLINE_SHIFT 16
14-
#define CTR_IMINLINE_SHIFT 0
15-
#define CTR_IMINLINE_MASK 0xf
16-
#define CTR_ERG_SHIFT 20
17-
#define CTR_CWG_SHIFT 24
18-
#define CTR_CWG_MASK 15
19-
#define CTR_IDC_SHIFT 28
20-
#define CTR_DIC_SHIFT 29
21-
22-
#define CTR_CACHE_MINLINE_MASK \
23-
(0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
24-
25-
#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
26-
27-
#define ICACHE_POLICY_VPIPT 0
28-
#define ICACHE_POLICY_RESERVED 1
29-
#define ICACHE_POLICY_VIPT 2
30-
#define ICACHE_POLICY_PIPT 3
31-
328
#define L1_CACHE_SHIFT (6)
339
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
3410

35-
3611
#define CLIDR_LOUU_SHIFT 27
3712
#define CLIDR_LOC_SHIFT 24
3813
#define CLIDR_LOUIS_SHIFT 21
@@ -55,6 +30,10 @@
5530
#include <linux/bitops.h>
5631
#include <linux/kasan-enabled.h>
5732

33+
#include <asm/cputype.h>
34+
#include <asm/mte-def.h>
35+
#include <asm/sysreg.h>
36+
5837
#ifdef CONFIG_KASAN_SW_TAGS
5938
#define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
6039
#elif defined(CONFIG_KASAN_HW_TAGS)
@@ -66,6 +45,12 @@ static inline unsigned int arch_slab_minalign(void)
6645
#define arch_slab_minalign() arch_slab_minalign()
6746
#endif
6847

48+
#define CTR_CACHE_MINLINE_MASK \
49+
(0xf << CTR_EL0_DMINLINE_SHIFT | \
50+
CTR_EL0_IMINLINE_MASK << CTR_EL0_IMINLINE_SHIFT)
51+
52+
#define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
53+
6954
#define ICACHEF_ALIASING 0
7055
#define ICACHEF_VPIPT 1
7156
extern unsigned long __icache_flags;
@@ -86,7 +71,7 @@ static __always_inline int icache_is_vpipt(void)
8671

8772
static inline u32 cache_type_cwg(void)
8873
{
89-
return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
74+
return (read_cpuid_cachetype() >> CTR_EL0_CWG_SHIFT) & CTR_EL0_CWG_MASK;
9075
}
9176

9277
#define __read_mostly __section(".data..read_mostly")
@@ -120,12 +105,12 @@ static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
120105
{
121106
u32 ctr = read_cpuid_cachetype();
122107

123-
if (!(ctr & BIT(CTR_IDC_SHIFT))) {
108+
if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) {
124109
u64 clidr = read_sysreg(clidr_el1);
125110

126111
if (CLIDR_LOC(clidr) == 0 ||
127112
(CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
128-
ctr |= BIT(CTR_IDC_SHIFT);
113+
ctr |= BIT(CTR_EL0_IDC_SHIFT);
129114
}
130115

131116
return ctr;

‎arch/arm64/include/asm/cpufeature.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -673,7 +673,7 @@ static inline bool supports_clearbhb(int scope)
673673
isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
674674

675675
return cpuid_feature_extract_unsigned_field(isar2,
676-
ID_AA64ISAR2_CLEARBHB_SHIFT);
676+
ID_AA64ISAR2_EL1_BC_SHIFT);
677677
}
678678

679679
const struct cpumask *system_32bit_el0_cpumask(void);

‎arch/arm64/include/asm/el2_setup.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@
161161
mov x1, #0 // SMCR controls
162162

163163
mrs_s x2, SYS_ID_AA64SMFR0_EL1
164-
ubfx x2, x2, #ID_AA64SMFR0_FA64_SHIFT, #1 // Full FP in SM?
164+
ubfx x2, x2, #ID_AA64SMFR0_EL1_FA64_SHIFT, #1 // Full FP in SM?
165165
cbz x2, .Lskip_sme_fa64_\@
166166

167167
orr x1, x1, SMCR_ELx_FA64_MASK

‎arch/arm64/include/asm/sysreg.h

Lines changed: 5 additions & 119 deletions
Original file line numberDiff line numberDiff line change
@@ -192,18 +192,13 @@
192192

193193
#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
194194
#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
195-
#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
196-
#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4, 5)
197195

198196
#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
199197
#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
200198

201199
#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
202200
#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
203201

204-
#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
205-
#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)
206-
207202
#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
208203
#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
209204
#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
@@ -410,12 +405,6 @@
410405
#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
411406
#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
412407

413-
#define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0)
414-
#define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1)
415-
#define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
416-
#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
417-
#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
418-
419408
#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
420409
#define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
421410

@@ -454,16 +443,12 @@
454443
#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
455444

456445
#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
457-
#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4)
458446
#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
459447

460448
#define SMIDR_EL1_IMPLEMENTER_SHIFT 24
461449
#define SMIDR_EL1_SMPS_SHIFT 15
462450
#define SMIDR_EL1_AFFINITY_SHIFT 0
463451

464-
#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
465-
#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
466-
467452
#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
468453
#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
469454

@@ -704,66 +689,6 @@
704689
/* Position the attr at the correct index */
705690
#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
706691

707-
/* id_aa64isar1 */
708-
#define ID_AA64ISAR1_I8MM_SHIFT 52
709-
#define ID_AA64ISAR1_DGH_SHIFT 48
710-
#define ID_AA64ISAR1_BF16_SHIFT 44
711-
#define ID_AA64ISAR1_SPECRES_SHIFT 40
712-
#define ID_AA64ISAR1_SB_SHIFT 36
713-
#define ID_AA64ISAR1_FRINTTS_SHIFT 32
714-
#define ID_AA64ISAR1_GPI_SHIFT 28
715-
#define ID_AA64ISAR1_GPA_SHIFT 24
716-
#define ID_AA64ISAR1_LRCPC_SHIFT 20
717-
#define ID_AA64ISAR1_FCMA_SHIFT 16
718-
#define ID_AA64ISAR1_JSCVT_SHIFT 12
719-
#define ID_AA64ISAR1_API_SHIFT 8
720-
#define ID_AA64ISAR1_APA_SHIFT 4
721-
#define ID_AA64ISAR1_DPB_SHIFT 0
722-
723-
#define ID_AA64ISAR1_APA_NI 0x0
724-
#define ID_AA64ISAR1_APA_ARCHITECTED 0x1
725-
#define ID_AA64ISAR1_APA_ARCH_EPAC 0x2
726-
#define ID_AA64ISAR1_APA_ARCH_EPAC2 0x3
727-
#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC 0x4
728-
#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB 0x5
729-
#define ID_AA64ISAR1_API_NI 0x0
730-
#define ID_AA64ISAR1_API_IMP_DEF 0x1
731-
#define ID_AA64ISAR1_API_IMP_DEF_EPAC 0x2
732-
#define ID_AA64ISAR1_API_IMP_DEF_EPAC2 0x3
733-
#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC 0x4
734-
#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB 0x5
735-
#define ID_AA64ISAR1_GPA_NI 0x0
736-
#define ID_AA64ISAR1_GPA_ARCHITECTED 0x1
737-
#define ID_AA64ISAR1_GPI_NI 0x0
738-
#define ID_AA64ISAR1_GPI_IMP_DEF 0x1
739-
740-
/* id_aa64isar2 */
741-
#define ID_AA64ISAR2_CLEARBHB_SHIFT 28
742-
#define ID_AA64ISAR2_APA3_SHIFT 12
743-
#define ID_AA64ISAR2_GPA3_SHIFT 8
744-
#define ID_AA64ISAR2_RPRES_SHIFT 4
745-
#define ID_AA64ISAR2_WFXT_SHIFT 0
746-
747-
#define ID_AA64ISAR2_RPRES_8BIT 0x0
748-
#define ID_AA64ISAR2_RPRES_12BIT 0x1
749-
/*
750-
* Value 0x1 has been removed from the architecture, and is
751-
* reserved, but has not yet been removed from the ARM ARM
752-
* as of ARM DDI 0487G.b.
753-
*/
754-
#define ID_AA64ISAR2_WFXT_NI 0x0
755-
#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2
756-
757-
#define ID_AA64ISAR2_APA3_NI 0x0
758-
#define ID_AA64ISAR2_APA3_ARCHITECTED 0x1
759-
#define ID_AA64ISAR2_APA3_ARCH_EPAC 0x2
760-
#define ID_AA64ISAR2_APA3_ARCH_EPAC2 0x3
761-
#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC 0x4
762-
#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC_CMB 0x5
763-
764-
#define ID_AA64ISAR2_GPA3_NI 0x0
765-
#define ID_AA64ISAR2_GPA3_ARCHITECTED 0x1
766-
767692
/* id_aa64pfr0 */
768693
#define ID_AA64PFR0_CSV3_SHIFT 60
769694
#define ID_AA64PFR0_CSV2_SHIFT 56
@@ -811,45 +736,6 @@
811736
#define ID_AA64PFR1_MTE 0x2
812737
#define ID_AA64PFR1_MTE_ASYMM 0x3
813738

814-
/* id_aa64zfr0 */
815-
#define ID_AA64ZFR0_F64MM_SHIFT 56
816-
#define ID_AA64ZFR0_F32MM_SHIFT 52
817-
#define ID_AA64ZFR0_I8MM_SHIFT 44
818-
#define ID_AA64ZFR0_SM4_SHIFT 40
819-
#define ID_AA64ZFR0_SHA3_SHIFT 32
820-
#define ID_AA64ZFR0_BF16_SHIFT 20
821-
#define ID_AA64ZFR0_BITPERM_SHIFT 16
822-
#define ID_AA64ZFR0_AES_SHIFT 4
823-
#define ID_AA64ZFR0_SVEVER_SHIFT 0
824-
825-
#define ID_AA64ZFR0_F64MM 0x1
826-
#define ID_AA64ZFR0_F32MM 0x1
827-
#define ID_AA64ZFR0_I8MM 0x1
828-
#define ID_AA64ZFR0_BF16 0x1
829-
#define ID_AA64ZFR0_SM4 0x1
830-
#define ID_AA64ZFR0_SHA3 0x1
831-
#define ID_AA64ZFR0_BITPERM 0x1
832-
#define ID_AA64ZFR0_AES 0x1
833-
#define ID_AA64ZFR0_AES_PMULL 0x2
834-
#define ID_AA64ZFR0_SVEVER_SVE2 0x1
835-
836-
/* id_aa64smfr0 */
837-
#define ID_AA64SMFR0_FA64_SHIFT 63
838-
#define ID_AA64SMFR0_I16I64_SHIFT 52
839-
#define ID_AA64SMFR0_F64F64_SHIFT 48
840-
#define ID_AA64SMFR0_I8I32_SHIFT 36
841-
#define ID_AA64SMFR0_F16F32_SHIFT 35
842-
#define ID_AA64SMFR0_B16F32_SHIFT 34
843-
#define ID_AA64SMFR0_F32F32_SHIFT 32
844-
845-
#define ID_AA64SMFR0_FA64 0x1
846-
#define ID_AA64SMFR0_I16I64 0xf
847-
#define ID_AA64SMFR0_F64F64 0x1
848-
#define ID_AA64SMFR0_I8I32 0xf
849-
#define ID_AA64SMFR0_F16F32 0x1
850-
#define ID_AA64SMFR0_B16F32 0x1
851-
#define ID_AA64SMFR0_F32F32 0x1
852-
853739
/* id_aa64mmfr0 */
854740
#define ID_AA64MMFR0_ECV_SHIFT 60
855741
#define ID_AA64MMFR0_FGT_SHIFT 56
@@ -1084,9 +970,6 @@
1084970
#define MVFR2_FPMISC_SHIFT 4
1085971
#define MVFR2_SIMDMISC_SHIFT 0
1086972

1087-
#define DCZID_DZP_SHIFT 4
1088-
#define DCZID_BS_SHIFT 0
1089-
1090973
#define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
1091974
#define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
1092975

@@ -1121,8 +1004,8 @@
11211004
#define SYS_RGSR_EL1_SEED_MASK 0xffffUL
11221005

11231006
/* GMID_EL1 field definitions */
1124-
#define SYS_GMID_EL1_BS_SHIFT 0
1125-
#define SYS_GMID_EL1_BS_SIZE 4
1007+
#define GMID_EL1_BS_SHIFT 0
1008+
#define GMID_EL1_BS_SIZE 4
11261009

11271010
/* TFSR{,E0}_EL1 bit definitions */
11281011
#define SYS_TFSR_EL1_TF0_SHIFT 0
@@ -1324,6 +1207,9 @@
13241207

13251208
#endif
13261209

1210+
#define SYS_FIELD_GET(reg, field, val) \
1211+
FIELD_GET(reg##_##field##_MASK, val)
1212+
13271213
#define SYS_FIELD_PREP(reg, field, val) \
13281214
FIELD_PREP(reg##_##field##_MASK, val)
13291215

‎arch/arm64/kernel/alternative.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@ static void clean_dcache_range_nopatch(u64 start, u64 end)
121121

122122
ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
123123
d_size = 4 << cpuid_feature_extract_unsigned_field(ctr_el0,
124-
CTR_DMINLINE_SHIFT);
124+
CTR_EL0_DminLine_SHIFT);
125125
cur = start & ~(d_size - 1);
126126
do {
127127
/*

‎arch/arm64/kernel/cpu_errata.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,7 @@ has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
187187
int scope)
188188
{
189189
u32 midr = read_cpuid_id();
190-
bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
190+
bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT);
191191
const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
192192

193193
WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

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