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torvaldstorvalds
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Merge tag 'drm-fixes-2024-04-26' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Regular weekly merge request, mostly amdgpu and misc bits in xe/etnaviv/gma500 and some core changes. Nothing too outlandish, seems to be about normal for this time of release. atomic-helpers: - Fix memory leak in drm_format_conv_state_copy() fbdev: - fbdefio: Fix address calculation amdgpu: - Suspend/resume fix - Don't expose gpu_od directory if it's empty - SDMA 4.4.2 fix - VPE fix - BO eviction fix - UMSCH fix - SMU 13.0.6 reset fixes - GPUVM flush accounting fix - SDMA 5.2 fix - Fix possible UAF in mes code amdkfd: - Eviction fence handling fix - Fix memory leak when GPU memory allocation fails - Fix dma-buf validation - Fix rescheduling of restore worker - SVM fix gma500: - Fix crash during boot etnaviv: - fix GC7000 TX clock gating - revert NPU UAPI changes xe: - Fix error paths on managed allocations - Fix PF/VF relay messages" * tag 'drm-fixes-2024-04-26' of https://gitlab.freedesktop.org/drm/kernel: (23 commits) Revert "drm/etnaviv: Expose a few more chipspecs to userspace" drm/etnaviv: fix tx clock gating on some GC7000 variants drm/xe/guc: Fix arguments passed to relay G2H handlers drm/xe: call free_gsc_pkt only once on action add failure drm/xe: Remove sysfs only once on action add failure fbdev: fix incorrect address computation in deferred IO drm/amdgpu/mes: fix use-after-free issue drm/amdgpu/sdma5.2: use legacy HDP flush for SDMA2/3 drm/amdgpu: Fix the ring buffer size for queue VM flush drm/amdkfd: Add VRAM accounting for SVM migration drm/amd/pm: Restore config space after reset drm/amdgpu/umsch: don't execute umsch test when GPU is in reset/suspend drm/amdkfd: Fix rescheduling of restore worker drm/amdgpu: Update BO eviction priorities drm/amdgpu/vpe: fix vpe dpm setup failed drm/amdgpu: Assign correct bits for SDMA HDP flush drm/amdgpu/pm: Remove gpu_od if it's an empty directory drm/amdkfd: make sure VM is ready for updating operations drm/amdgpu: Fix leak when GPU memory allocation fails drm/amdkfd: Fix eviction fence handling ...
2 parents c942a0c + 3a85340 commit 61ef620

32 files changed

+131
-243
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

Lines changed: 21 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1854,6 +1854,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
18541854
err_bo_create:
18551855
amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
18561856
err_reserve_limit:
1857+
amdgpu_sync_free(&(*mem)->sync);
18571858
mutex_destroy(&(*mem)->lock);
18581859
if (gobj)
18591860
drm_gem_object_put(gobj);
@@ -2900,13 +2901,12 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu *
29002901

29012902
amdgpu_sync_create(&sync_obj);
29022903

2903-
/* Validate BOs and map them to GPUVM (update VM page tables). */
2904+
/* Validate BOs managed by KFD */
29042905
list_for_each_entry(mem, &process_info->kfd_bo_list,
29052906
validate_list) {
29062907

29072908
struct amdgpu_bo *bo = mem->bo;
29082909
uint32_t domain = mem->domain;
2909-
struct kfd_mem_attachment *attachment;
29102910
struct dma_resv_iter cursor;
29112911
struct dma_fence *fence;
29122912

@@ -2931,6 +2931,25 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu *
29312931
goto validate_map_fail;
29322932
}
29332933
}
2934+
}
2935+
2936+
if (failed_size)
2937+
pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2938+
2939+
/* Validate PDs, PTs and evicted DMABuf imports last. Otherwise BO
2940+
* validations above would invalidate DMABuf imports again.
2941+
*/
2942+
ret = process_validate_vms(process_info, &exec.ticket);
2943+
if (ret) {
2944+
pr_debug("Validating VMs failed, ret: %d\n", ret);
2945+
goto validate_map_fail;
2946+
}
2947+
2948+
/* Update mappings managed by KFD. */
2949+
list_for_each_entry(mem, &process_info->kfd_bo_list,
2950+
validate_list) {
2951+
struct kfd_mem_attachment *attachment;
2952+
29342953
list_for_each_entry(attachment, &mem->attachments, list) {
29352954
if (!attachment->is_mapped)
29362955
continue;
@@ -2947,18 +2966,6 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu *
29472966
}
29482967
}
29492968

2950-
if (failed_size)
2951-
pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2952-
2953-
/* Validate PDs, PTs and evicted DMABuf imports last. Otherwise BO
2954-
* validations above would invalidate DMABuf imports again.
2955-
*/
2956-
ret = process_validate_vms(process_info, &exec.ticket);
2957-
if (ret) {
2958-
pr_debug("Validating VMs failed, ret: %d\n", ret);
2959-
goto validate_map_fail;
2960-
}
2961-
29622969
/* Update mappings not managed by KFD */
29632970
list_for_each_entry(peer_vm, &process_info->vm_list_head,
29642971
vm_list_node) {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1132,6 +1132,7 @@ void amdgpu_mes_remove_ring(struct amdgpu_device *adev,
11321132
return;
11331133

11341134
amdgpu_mes_remove_hw_queue(adev, ring->hw_queue_id);
1135+
del_timer_sync(&ring->fence_drv.fallback_timer);
11351136
amdgpu_ring_fini(ring);
11361137
kfree(ring);
11371138
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -605,6 +605,8 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
605605
else
606606
amdgpu_bo_placement_from_domain(bo, bp->domain);
607607
if (bp->type == ttm_bo_type_kernel)
608+
bo->tbo.priority = 2;
609+
else if (!(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE))
608610
bo->tbo.priority = 1;
609611

610612
if (!bp->destroy)

‎drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -774,6 +774,9 @@ static int umsch_mm_late_init(void *handle)
774774
{
775775
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
776776

777+
if (amdgpu_in_reset(adev) || adev->in_s0ix || adev->in_suspend)
778+
return 0;
779+
777780
return umsch_mm_test(adev);
778781
}
779782

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -205,7 +205,7 @@ int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)
205205
dpm_ctl &= 0xfffffffe; /* Disable DPM */
206206
WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
207207
dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__);
208-
return 0;
208+
return -EINVAL;
209209
}
210210

211211
int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9186,7 +9186,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
91869186
7 + /* PIPELINE_SYNC */
91879187
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
91889188
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9189-
2 + /* VM_FLUSH */
9189+
4 + /* VM_FLUSH */
91909190
8 + /* FENCE for VM_FLUSH */
91919191
20 + /* GDS switch */
91929192
4 + /* double SWITCH_BUFFER,
@@ -9276,7 +9276,6 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
92769276
7 + /* gfx_v10_0_ring_emit_pipeline_sync */
92779277
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
92789278
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9279-
2 + /* gfx_v10_0_ring_emit_vm_flush */
92809279
8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
92819280
.emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
92829281
.emit_ib = gfx_v10_0_ring_emit_ib_compute,

‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6192,7 +6192,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
61926192
7 + /* PIPELINE_SYNC */
61936193
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
61946194
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6195-
2 + /* VM_FLUSH */
6195+
4 + /* VM_FLUSH */
61966196
8 + /* FENCE for VM_FLUSH */
61976197
20 + /* GDS switch */
61986198
5 + /* COND_EXEC */
@@ -6278,7 +6278,6 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {
62786278
7 + /* gfx_v11_0_ring_emit_pipeline_sync */
62796279
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
62806280
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6281-
2 + /* gfx_v11_0_ring_emit_vm_flush */
62826281
8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */
62836282
.emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
62846283
.emit_ib = gfx_v11_0_ring_emit_ib_compute,

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6981,7 +6981,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
69816981
7 + /* gfx_v9_0_ring_emit_pipeline_sync */
69826982
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
69836983
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6984-
2 + /* gfx_v9_0_ring_emit_vm_flush */
69856984
8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
69866985
7 + /* gfx_v9_0_emit_mem_sync */
69876986
5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
@@ -7019,7 +7018,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
70197018
7 + /* gfx_v9_0_ring_emit_pipeline_sync */
70207019
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
70217020
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
7022-
2 + /* gfx_v9_0_ring_emit_vm_flush */
70237021
8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
70247022
.emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
70257023
.emit_fence = gfx_v9_0_ring_emit_fence_kiq,

‎drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -368,7 +368,8 @@ static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
368368
u32 ref_and_mask = 0;
369369
const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
370370

371-
ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
371+
ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0
372+
<< (ring->me % adev->sdma.num_inst_per_aid);
372373

373374
sdma_v4_4_2_wait_reg_mem(ring, 0, 1,
374375
adev->nbio.funcs->get_hdp_flush_done_offset(adev),

‎drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

Lines changed: 15 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -280,17 +280,21 @@ static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
280280
u32 ref_and_mask = 0;
281281
const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
282282

283-
ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
284-
285-
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
286-
SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
287-
SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
288-
amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
289-
amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
290-
amdgpu_ring_write(ring, ref_and_mask); /* reference */
291-
amdgpu_ring_write(ring, ref_and_mask); /* mask */
292-
amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
293-
SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
283+
if (ring->me > 1) {
284+
amdgpu_asic_flush_hdp(adev, ring);
285+
} else {
286+
ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
287+
288+
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
289+
SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
290+
SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
291+
amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
292+
amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
293+
amdgpu_ring_write(ring, ref_and_mask); /* reference */
294+
amdgpu_ring_write(ring, ref_and_mask); /* mask */
295+
amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
296+
SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
297+
}
294298
}
295299

296300
/**

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