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arm64: dts: sparx5: Add i2c devices, i2c muxes
This patch adds i2c devices and muxes to the Sparx5 reference boards. Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Alexandre Belloni <[email protected]> Signed-off-by: Lars Povlsen <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
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‎arch/arm64/boot/dts/microchip/sparx5.dtsi

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@@ -170,6 +170,44 @@
170170
pins = "GPIO_26", "GPIO_27";
171171
function = "uart2";
172172
};
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i2c_pins: i2c-pins {
175+
pins = "GPIO_14", "GPIO_15";
176+
function = "twi";
177+
};
178+
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i2c2_pins: i2c2-pins {
180+
pins = "GPIO_28", "GPIO_29";
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function = "twi2";
182+
};
183+
};
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i2c0: i2c@600101000 {
186+
compatible = "snps,designware-i2c";
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status = "disabled";
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pinctrl-0 = <&i2c_pins>;
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pinctrl-names = "default";
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reg = <0x6 0x00101000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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i2c-sda-hold-time-ns = <300>;
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clock-frequency = <100000>;
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clocks = <&ahb_clk>;
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};
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i2c1: i2c@600103000 {
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compatible = "snps,designware-i2c";
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status = "disabled";
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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reg = <0x6 0x00103000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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i2c-sda-hold-time-ns = <300>;
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clock-frequency = <100000>;
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clocks = <&ahb_clk>;
173211
};
174212
};
175213
};

‎arch/arm64/boot/dts/microchip/sparx5_pcb125.dts

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@@ -15,3 +15,7 @@
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reg = <0x00000000 0x00000000 0x10000000>;
1616
};
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};
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&i2c1 {
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status = "okay";
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};

‎arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi

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@@ -7,9 +7,246 @@
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#include "sparx5_pcb_common.dtsi"
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/{
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aliases {
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i2c0 = &i2c0;
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i2c100 = &i2c100;
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i2c101 = &i2c101;
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i2c102 = &i2c102;
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i2c103 = &i2c103;
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i2c104 = &i2c104;
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i2c105 = &i2c105;
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i2c106 = &i2c106;
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i2c107 = &i2c107;
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i2c108 = &i2c108;
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i2c109 = &i2c109;
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i2c110 = &i2c110;
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i2c111 = &i2c111;
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i2c112 = &i2c112;
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i2c113 = &i2c113;
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i2c114 = &i2c114;
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i2c115 = &i2c115;
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i2c116 = &i2c116;
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i2c117 = &i2c117;
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i2c118 = &i2c118;
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i2c119 = &i2c119;
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};
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1034
gpio-restart {
1135
compatible = "gpio-restart";
1236
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
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priority = <200>;
1438
};
1539
};
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&gpio {
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i2cmux_pins_i: i2cmux-pins-i {
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pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
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"GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35",
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"GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57";
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function = "twi_scl_m";
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output-low;
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};
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i2cmux_0: i2cmux-0 {
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pins = "GPIO_16";
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function = "twi_scl_m";
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output-high;
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};
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i2cmux_1: i2cmux-1 {
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pins = "GPIO_17";
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function = "twi_scl_m";
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output-high;
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};
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i2cmux_2: i2cmux-2 {
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pins = "GPIO_18";
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function = "twi_scl_m";
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output-high;
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};
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i2cmux_3: i2cmux-3 {
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pins = "GPIO_19";
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function = "twi_scl_m";
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output-high;
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};
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i2cmux_4: i2cmux-4 {
70+
pins = "GPIO_20";
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function = "twi_scl_m";
72+
output-high;
73+
};
74+
i2cmux_5: i2cmux-5 {
75+
pins = "GPIO_22";
76+
function = "twi_scl_m";
77+
output-high;
78+
};
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i2cmux_6: i2cmux-6 {
80+
pins = "GPIO_36";
81+
function = "twi_scl_m";
82+
output-high;
83+
};
84+
i2cmux_7: i2cmux-7 {
85+
pins = "GPIO_35";
86+
function = "twi_scl_m";
87+
output-high;
88+
};
89+
i2cmux_8: i2cmux-8 {
90+
pins = "GPIO_50";
91+
function = "twi_scl_m";
92+
output-high;
93+
};
94+
i2cmux_9: i2cmux-9 {
95+
pins = "GPIO_51";
96+
function = "twi_scl_m";
97+
output-high;
98+
};
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i2cmux_10: i2cmux-10 {
100+
pins = "GPIO_56";
101+
function = "twi_scl_m";
102+
output-high;
103+
};
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i2cmux_11: i2cmux-11 {
105+
pins = "GPIO_57";
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function = "twi_scl_m";
107+
output-high;
108+
};
109+
};
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&axi {
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i2c0_imux: i2c0-imux@0 {
113+
compatible = "i2c-mux-pinctrl";
114+
#address-cells = <1>;
115+
#size-cells = <0>;
116+
i2c-parent = <&i2c0>;
117+
};
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i2c0_emux: i2c0-emux@0 {
119+
compatible = "i2c-mux-gpio";
120+
#address-cells = <1>;
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#size-cells = <0>;
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i2c-parent = <&i2c0>;
123+
};
124+
};
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&i2c0_imux {
127+
pinctrl-names =
128+
"i2c100", "i2c101", "i2c102", "i2c103",
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"i2c104", "i2c105", "i2c106", "i2c107",
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"i2c108", "i2c109", "i2c110", "i2c111", "idle";
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pinctrl-0 = <&i2cmux_0>;
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pinctrl-1 = <&i2cmux_1>;
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pinctrl-2 = <&i2cmux_2>;
134+
pinctrl-3 = <&i2cmux_3>;
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pinctrl-4 = <&i2cmux_4>;
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pinctrl-5 = <&i2cmux_5>;
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pinctrl-6 = <&i2cmux_6>;
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pinctrl-7 = <&i2cmux_7>;
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pinctrl-8 = <&i2cmux_8>;
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pinctrl-9 = <&i2cmux_9>;
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pinctrl-10 = <&i2cmux_10>;
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pinctrl-11 = <&i2cmux_11>;
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pinctrl-12 = <&i2cmux_pins_i>;
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i2c100: i2c_sfp1 {
145+
reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
149+
i2c101: i2c_sfp2 {
150+
reg = <0x1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c102: i2c_sfp3 {
155+
reg = <0x2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
159+
i2c103: i2c_sfp4 {
160+
reg = <0x3>;
161+
#address-cells = <1>;
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#size-cells = <0>;
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};
164+
i2c104: i2c_sfp5 {
165+
reg = <0x4>;
166+
#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c105: i2c_sfp6 {
170+
reg = <0x5>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
174+
i2c106: i2c_sfp7 {
175+
reg = <0x6>;
176+
#address-cells = <1>;
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#size-cells = <0>;
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};
179+
i2c107: i2c_sfp8 {
180+
reg = <0x7>;
181+
#address-cells = <1>;
182+
#size-cells = <0>;
183+
};
184+
i2c108: i2c_sfp9 {
185+
reg = <0x8>;
186+
#address-cells = <1>;
187+
#size-cells = <0>;
188+
};
189+
i2c109: i2c_sfp10 {
190+
reg = <0x9>;
191+
#address-cells = <1>;
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#size-cells = <0>;
193+
};
194+
i2c110: i2c_sfp11 {
195+
reg = <0xa>;
196+
#address-cells = <1>;
197+
#size-cells = <0>;
198+
};
199+
i2c111: i2c_sfp12 {
200+
reg = <0xb>;
201+
#address-cells = <1>;
202+
#size-cells = <0>;
203+
};
204+
};
205+
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&i2c0_emux {
207+
mux-gpios = <&gpio 55 GPIO_ACTIVE_HIGH
208+
&gpio 60 GPIO_ACTIVE_HIGH
209+
&gpio 61 GPIO_ACTIVE_HIGH
210+
&gpio 54 GPIO_ACTIVE_HIGH>;
211+
idle-state = <0x8>;
212+
i2c112: i2c_sfp13 {
213+
reg = <0x0>;
214+
#address-cells = <1>;
215+
#size-cells = <0>;
216+
};
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i2c113: i2c_sfp14 {
218+
reg = <0x1>;
219+
#address-cells = <1>;
220+
#size-cells = <0>;
221+
};
222+
i2c114: i2c_sfp15 {
223+
reg = <0x2>;
224+
#address-cells = <1>;
225+
#size-cells = <0>;
226+
};
227+
i2c115: i2c_sfp16 {
228+
reg = <0x3>;
229+
#address-cells = <1>;
230+
#size-cells = <0>;
231+
};
232+
i2c116: i2c_sfp17 {
233+
reg = <0x4>;
234+
#address-cells = <1>;
235+
#size-cells = <0>;
236+
};
237+
i2c117: i2c_sfp18 {
238+
reg = <0x5>;
239+
#address-cells = <1>;
240+
#size-cells = <0>;
241+
};
242+
i2c118: i2c_sfp19 {
243+
reg = <0x6>;
244+
#address-cells = <1>;
245+
#size-cells = <0>;
246+
};
247+
i2c119: i2c_sfp20 {
248+
reg = <0x7>;
249+
#address-cells = <1>;
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#size-cells = <0>;
251+
};
252+
};

‎arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi

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Original file line numberDiff line numberDiff line change
@@ -7,9 +7,86 @@
77
#include "sparx5_pcb_common.dtsi"
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99
/{
10+
aliases {
11+
i2c0 = &i2c0;
12+
i2c152 = &i2c152;
13+
i2c153 = &i2c153;
14+
i2c154 = &i2c154;
15+
i2c155 = &i2c155;
16+
};
17+
1018
gpio-restart {
1119
compatible = "gpio-restart";
1220
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
1321
priority = <200>;
1422
};
1523
};
24+
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&gpio {
26+
i2cmux_pins_i: i2cmux-pins-i {
27+
pins = "GPIO_35", "GPIO_36",
28+
"GPIO_50", "GPIO_51";
29+
function = "twi_scl_m";
30+
output-low;
31+
};
32+
i2cmux_s29: i2cmux-0 {
33+
pins = "GPIO_35";
34+
function = "twi_scl_m";
35+
output-high;
36+
};
37+
i2cmux_s30: i2cmux-1 {
38+
pins = "GPIO_36";
39+
function = "twi_scl_m";
40+
output-high;
41+
};
42+
i2cmux_s31: i2cmux-2 {
43+
pins = "GPIO_50";
44+
function = "twi_scl_m";
45+
output-high;
46+
};
47+
i2cmux_s32: i2cmux-3 {
48+
pins = "GPIO_51";
49+
function = "twi_scl_m";
50+
output-high;
51+
};
52+
};
53+
54+
&axi {
55+
i2c0_imux: i2c0-imux@0 {
56+
compatible = "i2c-mux-pinctrl";
57+
#address-cells = <1>;
58+
#size-cells = <0>;
59+
i2c-parent = <&i2c0>;
60+
};
61+
};
62+
63+
&i2c0_imux {
64+
pinctrl-names =
65+
"i2c152", "i2c153", "i2c154", "i2c155",
66+
"idle";
67+
pinctrl-0 = <&i2cmux_s29>;
68+
pinctrl-1 = <&i2cmux_s30>;
69+
pinctrl-2 = <&i2cmux_s31>;
70+
pinctrl-3 = <&i2cmux_s32>;
71+
pinctrl-4 = <&i2cmux_pins_i>;
72+
i2c152: i2c_sfp1 {
73+
reg = <0x0>;
74+
#address-cells = <1>;
75+
#size-cells = <0>;
76+
};
77+
i2c153: i2c_sfp2 {
78+
reg = <0x1>;
79+
#address-cells = <1>;
80+
#size-cells = <0>;
81+
};
82+
i2c154: i2c_sfp3 {
83+
reg = <0x2>;
84+
#address-cells = <1>;
85+
#size-cells = <0>;
86+
};
87+
i2c155: i2c_sfp4 {
88+
reg = <0x3>;
89+
#address-cells = <1>;
90+
#size-cells = <0>;
91+
};
92+
};

‎arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi

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@@ -13,3 +13,7 @@
1313
&uart1 {
1414
status = "okay";
1515
};
16+
17+
&i2c0 {
18+
status = "okay";
19+
};

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