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47 | 47 |
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48 | 48 | #define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2)
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49 | 49 | #define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2)
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| 50 | +#define G12A_HHI_ISP_MEM_PD_REG0 (0x45 << 2) |
| 51 | +#define G12A_HHI_ISP_MEM_PD_REG1 (0x46 << 2) |
50 | 52 |
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51 | 53 | struct meson_ee_pwrc;
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52 | 54 | struct meson_ee_pwrc_domain;
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@@ -115,6 +117,13 @@ static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = {
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115 | 117 | .iso_mask = BIT(16) | BIT(17),
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116 | 118 | };
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117 | 119 |
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| 120 | +static struct meson_ee_pwrc_top_domain g12a_pwrc_isp = { |
| 121 | + .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, |
| 122 | + .sleep_mask = BIT(18) | BIT(19), |
| 123 | + .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, |
| 124 | + .iso_mask = BIT(18) | BIT(19), |
| 125 | +}; |
| 126 | + |
118 | 127 | /* Memory PD Domains */
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119 | 128 |
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120 | 129 | #define VPU_MEMPD(__reg) \
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@@ -231,6 +240,11 @@ static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
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231 | 240 | { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(31, 0) },
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232 | 241 | };
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233 | 242 |
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| 243 | +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_isp[] = { |
| 244 | + { G12A_HHI_ISP_MEM_PD_REG0, GENMASK(31, 0) }, |
| 245 | + { G12A_HHI_ISP_MEM_PD_REG1, GENMASK(31, 0) }, |
| 246 | +}; |
| 247 | + |
234 | 248 | #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \
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235 | 249 | { \
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236 | 250 | .name = __name, \
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@@ -269,6 +283,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
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269 | 283 | [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
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270 | 284 | [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna,
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271 | 285 | pwrc_ee_is_powered_off),
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| 286 | + [PWRC_G12A_ISP_ID] = TOP_PD("ISP", &g12a_pwrc_isp, g12a_pwrc_mem_isp, |
| 287 | + pwrc_ee_is_powered_off), |
272 | 288 | };
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273 | 289 |
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274 | 290 | static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
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