Skip to content

Commit 64dbc3d

Browse files
tmlindtmlind
committed
ARM: dts: Configure system timers for omap2
We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Let's also update the dts file to use #include while at it. Cc: [email protected] Cc: Aaro Koskinen <[email protected]> Cc: Grygorii Strashko <[email protected]> Cc: Keerthy <[email protected]> Cc: Lokesh Vutla <[email protected]> Cc: Rob Herring <[email protected]> Cc: Tero Kristo <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
1 parent 83bd18b commit 64dbc3d

9 files changed

+140
-128
lines changed

‎arch/arm/boot/dts/omap2.dtsi

Lines changed: 26 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -201,11 +201,32 @@
201201
clock-frequency = <48000000>;
202202
};
203203

204-
timer2: timer@4802a000 {
205-
compatible = "ti,omap2420-timer";
206-
reg = <0x4802a000 0x400>;
207-
interrupts = <38>;
208-
ti,hwmods = "timer2";
204+
timer2_target: target-module@4802a000 {
205+
compatible = "ti,sysc-omap2-timer", "ti,sysc";
206+
reg = <0x4802a000 0x4>,
207+
<0x4802a010 0x4>,
208+
<0x4802a014 0x4>;
209+
reg-names = "rev", "sysc", "syss";
210+
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
211+
SYSC_OMAP2_EMUFREE |
212+
SYSC_OMAP2_ENAWAKEUP |
213+
SYSC_OMAP2_SOFTRESET |
214+
SYSC_OMAP2_AUTOIDLE)>;
215+
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
216+
<SYSC_IDLE_NO>,
217+
<SYSC_IDLE_SMART>;
218+
ti,syss-mask = <1>;
219+
clocks = <&gpt2_fck>, <&gpt2_ick>;
220+
clock-names = "fck", "ick";
221+
#address-cells = <1>;
222+
#size-cells = <1>;
223+
ranges = <0x0 0x4802a000 0x1000>;
224+
225+
timer2: timer@0 {
226+
compatible = "ti,omap2420-timer";
227+
reg = <0 0x400>;
228+
interrupts = <38>;
229+
};
209230
};
210231

211232
timer3: timer@48078000 {

‎arch/arm/boot/dts/omap2420.dtsi

Lines changed: 56 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -68,10 +68,23 @@
6868
};
6969
};
7070

71-
counter32k: counter@4000 {
72-
compatible = "ti,omap-counter32k";
73-
reg = <0x4000 0x20>;
74-
ti,hwmods = "counter_32k";
71+
target-module@4000 {
72+
compatible = "ti,sysc-omap2", "ti,sysc";
73+
reg = <0x4000 0x4>,
74+
<0x4004 0x4>;
75+
reg-names = "rev", "sysc";
76+
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
77+
<SYSC_IDLE_NO>;
78+
clocks = <&func_32k_ck>;
79+
clock-names = "fck";
80+
#address-cells = <1>;
81+
#size-cells = <1>;
82+
ranges = <0x0 0x4000 0x1000>;
83+
84+
counter32k: counter@0 {
85+
compatible = "ti,omap-counter32k";
86+
reg = <0 0x20>;
87+
};
7588
};
7689
};
7790

@@ -194,12 +207,33 @@
194207
};
195208
};
196209

197-
timer1: timer@48028000 {
198-
compatible = "ti,omap2420-timer";
199-
reg = <0x48028000 0x400>;
200-
interrupts = <37>;
201-
ti,hwmods = "timer1";
202-
ti,timer-alwon;
210+
timer1_target: target-module@48028000 {
211+
compatible = "ti,sysc-omap2-timer", "ti,sysc";
212+
reg = <0x48028000 0x4>,
213+
<0x48028010 0x4>,
214+
<0x48028014 0x4>;
215+
reg-names = "rev", "sysc", "syss";
216+
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
217+
SYSC_OMAP2_EMUFREE |
218+
SYSC_OMAP2_ENAWAKEUP |
219+
SYSC_OMAP2_SOFTRESET |
220+
SYSC_OMAP2_AUTOIDLE)>;
221+
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
222+
<SYSC_IDLE_NO>,
223+
<SYSC_IDLE_SMART>;
224+
ti,syss-mask = <1>;
225+
clocks = <&gpt1_fck>, <&gpt1_ick>;
226+
clock-names = "fck", "ick";
227+
#address-cells = <1>;
228+
#size-cells = <1>;
229+
ranges = <0x0 0x48028000 0x1000>;
230+
231+
timer1: timer@0 {
232+
compatible = "ti,omap2420-timer";
233+
reg = <0 0x400>;
234+
interrupts = <37>;
235+
ti,timer-alwon;
236+
};
203237
};
204238

205239
wd_timer2: wdt@48022000 {
@@ -218,5 +252,15 @@
218252
compatible = "ti,omap2420-i2c";
219253
};
220254

221-
/include/ "omap24xx-clocks.dtsi"
222-
/include/ "omap2420-clocks.dtsi"
255+
#include "omap24xx-clocks.dtsi"
256+
#include "omap2420-clocks.dtsi"
257+
258+
/* Preferred always-on timer for clockevent */
259+
&timer1_target {
260+
ti,no-reset-on-init;
261+
ti,no-idle;
262+
timer@0 {
263+
assigned-clocks = <&gpt1_fck>;
264+
assigned-clock-parents = <&func_32k_ck>;
265+
};
266+
};

‎arch/arm/boot/dts/omap2430.dtsi

Lines changed: 56 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -81,10 +81,23 @@
8181
};
8282
};
8383

84-
counter32k: counter@20000 {
85-
compatible = "ti,omap-counter32k";
86-
reg = <0x20000 0x20>;
87-
ti,hwmods = "counter_32k";
84+
target-module@20000 {
85+
compatible = "ti,sysc-omap2", "ti,sysc";
86+
reg = <0x20000 0x4>,
87+
<0x20004 0x4>;
88+
reg-names = "rev", "sysc";
89+
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
90+
<SYSC_IDLE_NO>;
91+
clocks = <&func_32k_ck>;
92+
clock-names = "fck";
93+
#address-cells = <1>;
94+
#size-cells = <1>;
95+
ranges = <0x0 0x20000 0x1000>;
96+
97+
counter32k: counter@0 {
98+
compatible = "ti,omap-counter32k";
99+
reg = <0 0x20>;
100+
};
88101
};
89102
};
90103

@@ -277,12 +290,33 @@
277290
};
278291
};
279292

280-
timer1: timer@49018000 {
281-
compatible = "ti,omap2420-timer";
282-
reg = <0x49018000 0x400>;
283-
interrupts = <37>;
284-
ti,hwmods = "timer1";
285-
ti,timer-alwon;
293+
timer1_target: target-module@49018000 {
294+
compatible = "ti,sysc-omap2-timer", "ti,sysc";
295+
reg = <0x49018000 0x4>,
296+
<0x49018010 0x4>,
297+
<0x49018014 0x4>;
298+
reg-names = "rev", "sysc", "syss";
299+
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
300+
SYSC_OMAP2_EMUFREE |
301+
SYSC_OMAP2_ENAWAKEUP |
302+
SYSC_OMAP2_SOFTRESET |
303+
SYSC_OMAP2_AUTOIDLE)>;
304+
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
305+
<SYSC_IDLE_NO>,
306+
<SYSC_IDLE_SMART>;
307+
ti,syss-mask = <1>;
308+
clocks = <&gpt1_fck>, <&gpt1_ick>;
309+
clock-names = "fck", "ick";
310+
#address-cells = <1>;
311+
#size-cells = <1>;
312+
ranges = <0x0 0x49018000 0x1000>;
313+
314+
timer1: timer@0 {
315+
compatible = "ti,omap2420-timer";
316+
reg = <0 0x400>;
317+
interrupts = <37>;
318+
ti,timer-alwon;
319+
};
286320
};
287321

288322
mcspi3: spi@480b8000 {
@@ -321,5 +355,15 @@
321355
compatible = "ti,omap2430-i2c";
322356
};
323357

324-
/include/ "omap24xx-clocks.dtsi"
325-
/include/ "omap2430-clocks.dtsi"
358+
#include "omap24xx-clocks.dtsi"
359+
#include "omap2430-clocks.dtsi"
360+
361+
/* Preferred always-on timer for clockevent */
362+
&timer1_target {
363+
ti,no-reset-on-init;
364+
ti,no-idle;
365+
timer@0 {
366+
assigned-clocks = <&gpt1_fck>;
367+
assigned-clock-parents = <&func_32k_ck>;
368+
};
369+
};

‎arch/arm/mach-omap2/board-generic.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
5050
.map_io = omap242x_map_io,
5151
.init_early = omap2420_init_early,
5252
.init_machine = omap_generic_init,
53-
.init_time = omap_init_time,
53+
.init_time = omap_init_time_of,
5454
.dt_compat = omap242x_boards_compat,
5555
.restart = omap2xxx_restart,
5656
MACHINE_END
@@ -67,7 +67,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
6767
.map_io = omap243x_map_io,
6868
.init_early = omap2430_init_early,
6969
.init_machine = omap_generic_init,
70-
.init_time = omap_init_time,
70+
.init_time = omap_init_time_of,
7171
.dt_compat = omap243x_boards_compat,
7272
.restart = omap2xxx_restart,
7373
MACHINE_END

‎arch/arm/mach-omap2/omap_hwmod_2420_data.c

Lines changed: 0 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -264,14 +264,6 @@ static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
264264
.user = OCP_USER_MPU | OCP_USER_SDMA,
265265
};
266266

267-
/* l4_wkup -> timer1 */
268-
static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
269-
.master = &omap2xxx_l4_wkup_hwmod,
270-
.slave = &omap2xxx_timer1_hwmod,
271-
.clk = "gpt1_ick",
272-
.user = OCP_USER_MPU | OCP_USER_SDMA,
273-
};
274-
275267
/* l4_wkup -> wd_timer2 */
276268
static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
277269
.master = &omap2xxx_l4_wkup_hwmod,
@@ -352,15 +344,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
352344
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
353345
};
354346

355-
356-
/* l4_wkup -> 32ksync_counter */
357-
static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
358-
.master = &omap2xxx_l4_wkup_hwmod,
359-
.slave = &omap2xxx_counter_32k_hwmod,
360-
.clk = "sync_32k_ick",
361-
.user = OCP_USER_MPU | OCP_USER_SDMA,
362-
};
363-
364347
static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
365348
.master = &omap2xxx_l3_main_hwmod,
366349
.slave = &omap2xxx_gpmc_hwmod,
@@ -382,8 +365,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
382365
&omap2420_l4_core__i2c2,
383366
&omap2420_l3__iva,
384367
&omap2420_l3__dsp,
385-
&omap2420_l4_wkup__timer1,
386-
&omap2xxx_l4_core__timer2,
387368
&omap2xxx_l4_core__timer3,
388369
&omap2xxx_l4_core__timer4,
389370
&omap2xxx_l4_core__timer5,
@@ -411,7 +392,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
411392
&omap2xxx_l4_core__sham,
412393
&omap2xxx_l4_core__aes,
413394
&omap2420_l4_core__hdq1w,
414-
&omap2420_l4_wkup__counter_32k,
415395
&omap2420_l3__gpmc,
416396
NULL,
417397
};

‎arch/arm/mach-omap2/omap_hwmod_2430_data.c

Lines changed: 0 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -436,14 +436,6 @@ static struct omap_hwmod_ocp_if omap2430_l3__iva = {
436436
.user = OCP_USER_MPU | OCP_USER_SDMA,
437437
};
438438

439-
/* l4_wkup -> timer1 */
440-
static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
441-
.master = &omap2xxx_l4_wkup_hwmod,
442-
.slave = &omap2xxx_timer1_hwmod,
443-
.clk = "gpt1_ick",
444-
.user = OCP_USER_MPU | OCP_USER_SDMA,
445-
};
446-
447439
/* l4_wkup -> wd_timer2 */
448440
static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
449441
.master = &omap2xxx_l4_wkup_hwmod,
@@ -548,14 +540,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
548540
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
549541
};
550542

551-
/* l4_wkup -> 32ksync_counter */
552-
static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
553-
.master = &omap2xxx_l4_wkup_hwmod,
554-
.slave = &omap2xxx_counter_32k_hwmod,
555-
.clk = "sync_32k_ick",
556-
.user = OCP_USER_MPU | OCP_USER_SDMA,
557-
};
558-
559543
static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
560544
.master = &omap2xxx_l3_main_hwmod,
561545
.slave = &omap2xxx_gpmc_hwmod,
@@ -581,8 +565,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
581565
&omap2xxx_l4_core__mcspi2,
582566
&omap2430_l4_core__mcspi3,
583567
&omap2430_l3__iva,
584-
&omap2430_l4_wkup__timer1,
585-
&omap2xxx_l4_core__timer2,
586568
&omap2xxx_l4_core__timer3,
587569
&omap2xxx_l4_core__timer4,
588570
&omap2xxx_l4_core__timer5,
@@ -613,7 +595,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
613595
&omap2xxx_l4_core__rng,
614596
&omap2xxx_l4_core__sham,
615597
&omap2xxx_l4_core__aes,
616-
&omap2430_l4_wkup__counter_32k,
617598
&omap2430_l3__gpmc,
618599
NULL,
619600
};

‎arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -95,14 +95,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
9595
.user = OCP_USER_MPU | OCP_USER_SDMA,
9696
};
9797

98-
/* l4_core -> timer2 */
99-
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
100-
.master = &omap2xxx_l4_core_hwmod,
101-
.slave = &omap2xxx_timer2_hwmod,
102-
.clk = "gpt2_ick",
103-
.user = OCP_USER_MPU | OCP_USER_SDMA,
104-
};
105-
10698
/* l4_core -> timer3 */
10799
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
108100
.master = &omap2xxx_l4_core_hwmod,

‎arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

Lines changed: 0 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -195,36 +195,6 @@ struct omap_hwmod omap2xxx_iva_hwmod = {
195195
.class = &iva_hwmod_class,
196196
};
197197

198-
/* timer1 */
199-
struct omap_hwmod omap2xxx_timer1_hwmod = {
200-
.name = "timer1",
201-
.main_clk = "gpt1_fck",
202-
.prcm = {
203-
.omap2 = {
204-
.module_offs = WKUP_MOD,
205-
.idlest_reg_id = 1,
206-
.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
207-
},
208-
},
209-
.class = &omap2xxx_timer_hwmod_class,
210-
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
211-
};
212-
213-
/* timer2 */
214-
struct omap_hwmod omap2xxx_timer2_hwmod = {
215-
.name = "timer2",
216-
.main_clk = "gpt2_fck",
217-
.prcm = {
218-
.omap2 = {
219-
.module_offs = CORE_MOD,
220-
.idlest_reg_id = 1,
221-
.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
222-
},
223-
},
224-
.class = &omap2xxx_timer_hwmod_class,
225-
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
226-
};
227-
228198
/* timer3 */
229199
struct omap_hwmod omap2xxx_timer3_hwmod = {
230200
.name = "timer3",
@@ -595,23 +565,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = {
595565
.class = &omap2xxx_mcspi_class,
596566
};
597567

598-
static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
599-
.name = "counter",
600-
};
601-
602-
struct omap_hwmod omap2xxx_counter_32k_hwmod = {
603-
.name = "counter_32k",
604-
.main_clk = "func_32k_ck",
605-
.prcm = {
606-
.omap2 = {
607-
.module_offs = WKUP_MOD,
608-
.idlest_reg_id = 1,
609-
.idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
610-
},
611-
},
612-
.class = &omap2xxx_counter_hwmod_class,
613-
};
614-
615568
/* gpmc */
616569
struct omap_hwmod omap2xxx_gpmc_hwmod = {
617570
.name = "gpmc",

0 commit comments

Comments
 (0)