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airliedairlied
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Merge tag 'drm-intel-fixes-2022-05-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
- fix for #5806: GPU hangs and display artifacts on 5.18-rc3 on Intel GM45 - reject DMC with out-of-spec MMIO (Cc: stable) - correctly mark guilty contexts on GuC reset. Signed-off-by: Dave Airlie <[email protected]> From: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 6e4a61c + 7b1d692 commit 64eea68

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+74
-16
lines changed

8 files changed

+74
-16
lines changed

‎drivers/gpu/drm/i915/display/intel_dmc.c

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -367,6 +367,44 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
367367
}
368368
}
369369

370+
static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
371+
const u32 *mmioaddr, u32 mmio_count,
372+
int header_ver, u8 dmc_id)
373+
{
374+
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
375+
u32 start_range, end_range;
376+
int i;
377+
378+
if (dmc_id >= DMC_FW_MAX) {
379+
drm_warn(&i915->drm, "Unsupported firmware id %u\n", dmc_id);
380+
return false;
381+
}
382+
383+
if (header_ver == 1) {
384+
start_range = DMC_MMIO_START_RANGE;
385+
end_range = DMC_MMIO_END_RANGE;
386+
} else if (dmc_id == DMC_FW_MAIN) {
387+
start_range = TGL_MAIN_MMIO_START;
388+
end_range = TGL_MAIN_MMIO_END;
389+
} else if (DISPLAY_VER(i915) >= 13) {
390+
start_range = ADLP_PIPE_MMIO_START;
391+
end_range = ADLP_PIPE_MMIO_END;
392+
} else if (DISPLAY_VER(i915) >= 12) {
393+
start_range = TGL_PIPE_MMIO_START(dmc_id);
394+
end_range = TGL_PIPE_MMIO_END(dmc_id);
395+
} else {
396+
drm_warn(&i915->drm, "Unknown mmio range for sanity check");
397+
return false;
398+
}
399+
400+
for (i = 0; i < mmio_count; i++) {
401+
if (mmioaddr[i] < start_range || mmioaddr[i] > end_range)
402+
return false;
403+
}
404+
405+
return true;
406+
}
407+
370408
static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
371409
const struct intel_dmc_header_base *dmc_header,
372410
size_t rem_size, u8 dmc_id)
@@ -436,6 +474,12 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
436474
return 0;
437475
}
438476

477+
if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count,
478+
dmc_header->header_ver, dmc_id)) {
479+
drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n");
480+
return 0;
481+
}
482+
439483
for (i = 0; i < mmio_count; i++) {
440484
dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
441485
dmc_info->mmiodata[i] = mmiodata[i];

‎drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1252,14 +1252,12 @@ static void *reloc_iomap(struct i915_vma *batch,
12521252
* Only attempt to pin the batch buffer to ggtt if the current batch
12531253
* is not inside ggtt, or the batch buffer is not misplaced.
12541254
*/
1255-
if (!i915_is_ggtt(batch->vm)) {
1255+
if (!i915_is_ggtt(batch->vm) ||
1256+
!i915_vma_misplaced(batch, 0, 0, PIN_MAPPABLE)) {
12561257
vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0,
12571258
PIN_MAPPABLE |
12581259
PIN_NONBLOCK /* NOWARN */ |
12591260
PIN_NOEVICT);
1260-
} else if (i915_vma_is_map_and_fenceable(batch)) {
1261-
__i915_vma_pin(batch);
1262-
vma = batch;
12631261
}
12641262

12651263
if (vma == ERR_PTR(-EDEADLK))

‎drivers/gpu/drm/i915/gt/intel_reset.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -806,7 +806,7 @@ static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
806806
__intel_engine_reset(engine, stalled_mask & engine->mask);
807807
local_bh_enable();
808808

809-
intel_uc_reset(&gt->uc, true);
809+
intel_uc_reset(&gt->uc, ALL_ENGINES);
810810

811811
intel_ggtt_restore_fences(gt->ggtt);
812812

‎drivers/gpu/drm/i915/gt/uc/intel_guc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -438,7 +438,7 @@ int intel_guc_global_policies_update(struct intel_guc *guc);
438438
void intel_guc_context_ban(struct intel_context *ce, struct i915_request *rq);
439439

440440
void intel_guc_submission_reset_prepare(struct intel_guc *guc);
441-
void intel_guc_submission_reset(struct intel_guc *guc, bool stalled);
441+
void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled);
442442
void intel_guc_submission_reset_finish(struct intel_guc *guc);
443443
void intel_guc_submission_cancel_requests(struct intel_guc *guc);
444444

‎drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1590,9 +1590,9 @@ __unwind_incomplete_requests(struct intel_context *ce)
15901590
spin_unlock_irqrestore(&sched_engine->lock, flags);
15911591
}
15921592

1593-
static void __guc_reset_context(struct intel_context *ce, bool stalled)
1593+
static void __guc_reset_context(struct intel_context *ce, intel_engine_mask_t stalled)
15941594
{
1595-
bool local_stalled;
1595+
bool guilty;
15961596
struct i915_request *rq;
15971597
unsigned long flags;
15981598
u32 head;
@@ -1620,22 +1620,22 @@ static void __guc_reset_context(struct intel_context *ce, bool stalled)
16201620
if (!intel_context_is_pinned(ce))
16211621
goto next_context;
16221622

1623-
local_stalled = false;
1623+
guilty = false;
16241624
rq = intel_context_find_active_request(ce);
16251625
if (!rq) {
16261626
head = ce->ring->tail;
16271627
goto out_replay;
16281628
}
16291629

16301630
if (i915_request_started(rq))
1631-
local_stalled = true;
1631+
guilty = stalled & ce->engine->mask;
16321632

16331633
GEM_BUG_ON(i915_active_is_idle(&ce->active));
16341634
head = intel_ring_wrap(ce->ring, rq->head);
16351635

1636-
__i915_request_reset(rq, local_stalled && stalled);
1636+
__i915_request_reset(rq, guilty);
16371637
out_replay:
1638-
guc_reset_state(ce, head, local_stalled && stalled);
1638+
guc_reset_state(ce, head, guilty);
16391639
next_context:
16401640
if (i != number_children)
16411641
ce = list_next_entry(ce, parallel.child_link);
@@ -1645,7 +1645,7 @@ static void __guc_reset_context(struct intel_context *ce, bool stalled)
16451645
intel_context_put(parent);
16461646
}
16471647

1648-
void intel_guc_submission_reset(struct intel_guc *guc, bool stalled)
1648+
void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled)
16491649
{
16501650
struct intel_context *ce;
16511651
unsigned long index;
@@ -4013,7 +4013,7 @@ static void guc_context_replay(struct intel_context *ce)
40134013
{
40144014
struct i915_sched_engine *sched_engine = ce->engine->sched_engine;
40154015

4016-
__guc_reset_context(ce, true);
4016+
__guc_reset_context(ce, ce->engine->mask);
40174017
tasklet_hi_schedule(&sched_engine->tasklet);
40184018
}
40194019

‎drivers/gpu/drm/i915/gt/uc/intel_uc.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -593,7 +593,7 @@ void intel_uc_reset_prepare(struct intel_uc *uc)
593593
__uc_sanitize(uc);
594594
}
595595

596-
void intel_uc_reset(struct intel_uc *uc, bool stalled)
596+
void intel_uc_reset(struct intel_uc *uc, intel_engine_mask_t stalled)
597597
{
598598
struct intel_guc *guc = &uc->guc;
599599

‎drivers/gpu/drm/i915/gt/uc/intel_uc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ void intel_uc_driver_late_release(struct intel_uc *uc);
4242
void intel_uc_driver_remove(struct intel_uc *uc);
4343
void intel_uc_init_mmio(struct intel_uc *uc);
4444
void intel_uc_reset_prepare(struct intel_uc *uc);
45-
void intel_uc_reset(struct intel_uc *uc, bool stalled);
45+
void intel_uc_reset(struct intel_uc *uc, intel_engine_mask_t stalled);
4646
void intel_uc_reset_finish(struct intel_uc *uc);
4747
void intel_uc_cancel_requests(struct intel_uc *uc);
4848
void intel_uc_suspend(struct intel_uc *uc);

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5501,6 +5501,22 @@
55015501
/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
55025502
#define DMC_MMIO_START_RANGE 0x80000
55035503
#define DMC_MMIO_END_RANGE 0x8FFFF
5504+
#define DMC_V1_MMIO_START_RANGE 0x80000
5505+
#define TGL_MAIN_MMIO_START 0x8F000
5506+
#define TGL_MAIN_MMIO_END 0x8FFFF
5507+
#define _TGL_PIPEA_MMIO_START 0x92000
5508+
#define _TGL_PIPEA_MMIO_END 0x93FFF
5509+
#define _TGL_PIPEB_MMIO_START 0x96000
5510+
#define _TGL_PIPEB_MMIO_END 0x97FFF
5511+
#define ADLP_PIPE_MMIO_START 0x5F000
5512+
#define ADLP_PIPE_MMIO_END 0x5FFFF
5513+
5514+
#define TGL_PIPE_MMIO_START(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\
5515+
_TGL_PIPEB_MMIO_START)
5516+
5517+
#define TGL_PIPE_MMIO_END(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\
5518+
_TGL_PIPEB_MMIO_END)
5519+
55045520
#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
55055521
#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
55065522
#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)

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