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Merge tag 'amd-drm-next-6.1-2022-09-30' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.1-2022-09-30: amdgpu: - RLC FW code cleanup - RLC fixes for GC 11.x - SMU 13.x fixes - CP FW code cleanup - SDMA FW code cleanup - GC 11.x fixes - DCN 3.2.x fixes - DCN 3.1.4 fixes - Misc fixes - RAS fixes - SR-IOV fixes - VCN 4.x fixes amdkfd: - GC 11.x fixes - Xnack fixes - UBSAN warning fix Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 4ae9f87 + b292caf commit 6589868

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82 files changed

+2116
-1987
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1053,6 +1053,10 @@ bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev)
10531053
{
10541054
if (adev->flags & AMD_IS_APU)
10551055
return false;
1056+
1057+
if (amdgpu_sriov_vf(adev))
1058+
return false;
1059+
10561060
return pm_suspend_target_state != PM_SUSPEND_TO_IDLE;
10571061
}
10581062

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -756,11 +756,7 @@ void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bo
756756
{
757757
struct ras_err_data err_data = {0, 0, 0, NULL};
758758

759-
/* CPU MCA will handle page retirement if connected_to_cpu is 1 */
760-
if (!adev->gmc.xgmi.connected_to_cpu)
761-
amdgpu_umc_poison_handler(adev, &err_data, reset);
762-
else if (reset)
763-
amdgpu_amdkfd_gpu_reset(adev);
759+
amdgpu_umc_poison_handler(adev, &err_data, reset);
764760
}
765761

766762
bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 29 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3154,7 +3154,8 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
31543154
continue;
31553155
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
31563156
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3157-
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
3157+
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3158+
(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
31583159

31593160
r = adev->ip_blocks[i].version->funcs->resume(adev);
31603161
if (r) {
@@ -4069,12 +4070,20 @@ static void amdgpu_device_evict_resources(struct amdgpu_device *adev)
40694070
int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
40704071
{
40714072
struct amdgpu_device *adev = drm_to_adev(dev);
4073+
int r = 0;
40724074

40734075
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
40744076
return 0;
40754077

40764078
adev->in_suspend = true;
40774079

4080+
if (amdgpu_sriov_vf(adev)) {
4081+
amdgpu_virt_fini_data_exchange(adev);
4082+
r = amdgpu_virt_request_full_gpu(adev, false);
4083+
if (r)
4084+
return r;
4085+
}
4086+
40784087
if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
40794088
DRM_WARN("smart shift update failed\n");
40804089

@@ -4098,6 +4107,9 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
40984107

40994108
amdgpu_device_ip_suspend_phase2(adev);
41004109

4110+
if (amdgpu_sriov_vf(adev))
4111+
amdgpu_virt_release_full_gpu(adev, false);
4112+
41014113
return 0;
41024114
}
41034115

@@ -4116,6 +4128,12 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
41164128
struct amdgpu_device *adev = drm_to_adev(dev);
41174129
int r = 0;
41184130

4131+
if (amdgpu_sriov_vf(adev)) {
4132+
r = amdgpu_virt_request_full_gpu(adev, true);
4133+
if (r)
4134+
return r;
4135+
}
4136+
41194137
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
41204138
return 0;
41214139

@@ -4130,6 +4148,13 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
41304148
}
41314149

41324150
r = amdgpu_device_ip_resume(adev);
4151+
4152+
/* no matter what r is, always need to properly release full GPU */
4153+
if (amdgpu_sriov_vf(adev)) {
4154+
amdgpu_virt_init_data_exchange(adev);
4155+
amdgpu_virt_release_full_gpu(adev, true);
4156+
}
4157+
41334158
if (r) {
41344159
dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
41354160
return r;
@@ -5576,9 +5601,9 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
55765601
~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
55775602
resource_size_t aper_limit =
55785603
adev->gmc.aper_base + adev->gmc.aper_size - 1;
5579-
bool p2p_access = !adev->gmc.xgmi.connected_to_cpu &&
5580-
!(pci_p2pdma_distance_many(adev->pdev,
5581-
&peer_adev->dev, 1, true) < 0);
5604+
bool p2p_access =
5605+
!adev->gmc.xgmi.connected_to_cpu &&
5606+
!(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
55825607

55835608
return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
55845609
adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&

‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -229,7 +229,7 @@ static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, ui
229229
return r;
230230
}
231231

232-
memcpy((u8 *)binary, (u8 *)fw->data, adev->mman.discovery_tmr_size);
232+
memcpy((u8 *)binary, (u8 *)fw->data, fw->size);
233233
release_firmware(fw);
234234

235235
return 0;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
5858
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
5959
int r;
6060

61-
if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, true) < 0)
61+
if (pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)
6262
attach->peer2peer = false;
6363

6464
r = pm_runtime_get_sync(adev_to_drm(adev)->dev);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -400,7 +400,6 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
400400
/* We are not protected by ring lock when reading the last sequence
401401
* but it's ok to report slightly wrong fence count here.
402402
*/
403-
amdgpu_fence_process(ring);
404403
emitted = 0x100000000ull;
405404
emitted -= atomic_read(&ring->fence_drv.last_seq);
406405
emitted += READ_ONCE(ring->fence_drv.sync_seq);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

Lines changed: 140 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@
2323
*
2424
*/
2525

26+
#include <linux/firmware.h>
2627
#include "amdgpu.h"
2728
#include "amdgpu_gfx.h"
2829
#include "amdgpu_rlc.h"
@@ -865,3 +866,142 @@ int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
865866
}
866867
return amdgpu_num_kcq;
867868
}
869+
870+
void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev,
871+
uint32_t ucode_id)
872+
{
873+
const struct gfx_firmware_header_v1_0 *cp_hdr;
874+
const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
875+
struct amdgpu_firmware_info *info = NULL;
876+
const struct firmware *ucode_fw;
877+
unsigned int fw_size;
878+
879+
switch (ucode_id) {
880+
case AMDGPU_UCODE_ID_CP_PFP:
881+
cp_hdr = (const struct gfx_firmware_header_v1_0 *)
882+
adev->gfx.pfp_fw->data;
883+
adev->gfx.pfp_fw_version =
884+
le32_to_cpu(cp_hdr->header.ucode_version);
885+
adev->gfx.pfp_feature_version =
886+
le32_to_cpu(cp_hdr->ucode_feature_version);
887+
ucode_fw = adev->gfx.pfp_fw;
888+
fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
889+
break;
890+
case AMDGPU_UCODE_ID_CP_RS64_PFP:
891+
cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
892+
adev->gfx.pfp_fw->data;
893+
adev->gfx.pfp_fw_version =
894+
le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
895+
adev->gfx.pfp_feature_version =
896+
le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
897+
ucode_fw = adev->gfx.pfp_fw;
898+
fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
899+
break;
900+
case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
901+
case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
902+
cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
903+
adev->gfx.pfp_fw->data;
904+
ucode_fw = adev->gfx.pfp_fw;
905+
fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
906+
break;
907+
case AMDGPU_UCODE_ID_CP_ME:
908+
cp_hdr = (const struct gfx_firmware_header_v1_0 *)
909+
adev->gfx.me_fw->data;
910+
adev->gfx.me_fw_version =
911+
le32_to_cpu(cp_hdr->header.ucode_version);
912+
adev->gfx.me_feature_version =
913+
le32_to_cpu(cp_hdr->ucode_feature_version);
914+
ucode_fw = adev->gfx.me_fw;
915+
fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
916+
break;
917+
case AMDGPU_UCODE_ID_CP_RS64_ME:
918+
cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
919+
adev->gfx.me_fw->data;
920+
adev->gfx.me_fw_version =
921+
le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
922+
adev->gfx.me_feature_version =
923+
le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
924+
ucode_fw = adev->gfx.me_fw;
925+
fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
926+
break;
927+
case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
928+
case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
929+
cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
930+
adev->gfx.me_fw->data;
931+
ucode_fw = adev->gfx.me_fw;
932+
fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
933+
break;
934+
case AMDGPU_UCODE_ID_CP_CE:
935+
cp_hdr = (const struct gfx_firmware_header_v1_0 *)
936+
adev->gfx.ce_fw->data;
937+
adev->gfx.ce_fw_version =
938+
le32_to_cpu(cp_hdr->header.ucode_version);
939+
adev->gfx.ce_feature_version =
940+
le32_to_cpu(cp_hdr->ucode_feature_version);
941+
ucode_fw = adev->gfx.ce_fw;
942+
fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
943+
break;
944+
case AMDGPU_UCODE_ID_CP_MEC1:
945+
cp_hdr = (const struct gfx_firmware_header_v1_0 *)
946+
adev->gfx.mec_fw->data;
947+
adev->gfx.mec_fw_version =
948+
le32_to_cpu(cp_hdr->header.ucode_version);
949+
adev->gfx.mec_feature_version =
950+
le32_to_cpu(cp_hdr->ucode_feature_version);
951+
ucode_fw = adev->gfx.mec_fw;
952+
fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
953+
le32_to_cpu(cp_hdr->jt_size) * 4;
954+
break;
955+
case AMDGPU_UCODE_ID_CP_MEC1_JT:
956+
cp_hdr = (const struct gfx_firmware_header_v1_0 *)
957+
adev->gfx.mec_fw->data;
958+
ucode_fw = adev->gfx.mec_fw;
959+
fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
960+
break;
961+
case AMDGPU_UCODE_ID_CP_MEC2:
962+
cp_hdr = (const struct gfx_firmware_header_v1_0 *)
963+
adev->gfx.mec2_fw->data;
964+
adev->gfx.mec2_fw_version =
965+
le32_to_cpu(cp_hdr->header.ucode_version);
966+
adev->gfx.mec2_feature_version =
967+
le32_to_cpu(cp_hdr->ucode_feature_version);
968+
ucode_fw = adev->gfx.mec2_fw;
969+
fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
970+
le32_to_cpu(cp_hdr->jt_size) * 4;
971+
break;
972+
case AMDGPU_UCODE_ID_CP_MEC2_JT:
973+
cp_hdr = (const struct gfx_firmware_header_v1_0 *)
974+
adev->gfx.mec2_fw->data;
975+
ucode_fw = adev->gfx.mec2_fw;
976+
fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
977+
break;
978+
case AMDGPU_UCODE_ID_CP_RS64_MEC:
979+
cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
980+
adev->gfx.mec_fw->data;
981+
adev->gfx.mec_fw_version =
982+
le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
983+
adev->gfx.mec_feature_version =
984+
le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
985+
ucode_fw = adev->gfx.mec_fw;
986+
fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
987+
break;
988+
case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
989+
case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
990+
case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
991+
case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
992+
cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
993+
adev->gfx.mec_fw->data;
994+
ucode_fw = adev->gfx.mec_fw;
995+
fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
996+
break;
997+
default:
998+
break;
999+
}
1000+
1001+
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1002+
info = &adev->firmware.ucode[ucode_id];
1003+
info->ucode_id = ucode_id;
1004+
info->fw = ucode_fw;
1005+
adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);
1006+
}
1007+
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -426,4 +426,6 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
426426
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
427427
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
428428
int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
429+
void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
430+
429431
#endif

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

Lines changed: 9 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -572,45 +572,15 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
572572
void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)
573573
{
574574
struct amdgpu_gmc *gmc = &adev->gmc;
575-
576-
switch (adev->ip_versions[GC_HWIP][0]) {
577-
case IP_VERSION(9, 0, 1):
578-
case IP_VERSION(9, 3, 0):
579-
case IP_VERSION(9, 4, 0):
580-
case IP_VERSION(9, 4, 1):
581-
case IP_VERSION(9, 4, 2):
582-
case IP_VERSION(10, 3, 3):
583-
case IP_VERSION(10, 3, 4):
584-
case IP_VERSION(10, 3, 5):
585-
case IP_VERSION(10, 3, 6):
586-
case IP_VERSION(10, 3, 7):
587-
/*
588-
* noretry = 0 will cause kfd page fault tests fail
589-
* for some ASICs, so set default to 1 for these ASICs.
590-
*/
591-
if (amdgpu_noretry == -1)
592-
gmc->noretry = 1;
593-
else
594-
gmc->noretry = amdgpu_noretry;
595-
break;
596-
default:
597-
/* Raven currently has issues with noretry
598-
* regardless of what we decide for other
599-
* asics, we should leave raven with
600-
* noretry = 0 until we root cause the
601-
* issues.
602-
*
603-
* default this to 0 for now, but we may want
604-
* to change this in the future for certain
605-
* GPUs as it can increase performance in
606-
* certain cases.
607-
*/
608-
if (amdgpu_noretry == -1)
609-
gmc->noretry = 0;
610-
else
611-
gmc->noretry = amdgpu_noretry;
612-
break;
613-
}
575+
uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
576+
bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) ||
577+
gc_ver == IP_VERSION(9, 3, 0) ||
578+
gc_ver == IP_VERSION(9, 4, 0) ||
579+
gc_ver == IP_VERSION(9, 4, 1) ||
580+
gc_ver == IP_VERSION(9, 4, 2) ||
581+
gc_ver >= IP_VERSION(10, 3, 0));
582+
583+
gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry;
614584
}
615585

616586
void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -222,6 +222,8 @@ struct mes_add_queue_input {
222222
uint64_t tba_addr;
223223
uint64_t tma_addr;
224224
uint32_t is_kfd_process;
225+
uint32_t is_aql_queue;
226+
uint32_t queue_size;
225227
};
226228

227229
struct mes_remove_queue_input {

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