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drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display
Collect the dipslay related mask under the display sub-structure in intel_device_info. Note that there is a slight change in behaviour in that we zero out .display entirely when !HAS_DISPLAY (aka. pipe_mask==0), so now we also zero out the other masks (although cpu_transocder_mask should already be zero of pipe_mask is zero). abox_mask is only used by the display core init when HAS_DISPLAY is true, so the actual behaviour of the system shouldn't change despite the zeroing of these masks. There is a lot more display stuff directly in device info that could be moved over. Maybe someone else will be inspired to do it... Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
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‎drivers/gpu/drm/i915/display/intel_display.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -372,15 +372,15 @@ enum hpd_pin {
372372

373373
#define for_each_pipe(__dev_priv, __p) \
374374
for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
375-
for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
375+
for_each_if(INTEL_INFO(__dev_priv)->display.pipe_mask & BIT(__p))
376376

377377
#define for_each_pipe_masked(__dev_priv, __p, __mask) \
378378
for_each_pipe(__dev_priv, __p) \
379379
for_each_if((__mask) & BIT(__p))
380380

381381
#define for_each_cpu_transcoder(__dev_priv, __t) \
382382
for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
383-
for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
383+
for_each_if (INTEL_INFO(__dev_priv)->display.cpu_transcoder_mask & BIT(__t))
384384

385385
#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
386386
for_each_cpu_transcoder(__dev_priv, __t) \

‎drivers/gpu/drm/i915/display/intel_display_power.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5370,7 +5370,7 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
53705370

53715371
static void icl_mbus_init(struct drm_i915_private *dev_priv)
53725372
{
5373-
unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask;
5373+
unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;
53745374
u32 mask, val, i;
53755375

53765376
if (IS_ALDERLAKE_P(dev_priv))
@@ -5830,7 +5830,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
58305830
enum intel_dram_type type = dev_priv->dram_info.type;
58315831
u8 num_channels = dev_priv->dram_info.num_channels;
58325832
const struct buddy_page_mask *table;
5833-
unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
5833+
unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask;
58345834
int config, i;
58355835

58365836
/* BW_BUDDY registers are not used on dgpu's beyond DG1 */

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1506,7 +1506,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
15061506
#define HAS_PSR_HW_TRACKING(dev_priv) \
15071507
(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
15081508
#define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
1509-
#define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1509+
#define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
15101510

15111511
#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
15121512
#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
@@ -1551,9 +1551,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
15511551
#define GT_FREQUENCY_MULTIPLIER 50
15521552
#define GEN9_FREQ_SCALER 3
15531553

1554-
#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1554+
#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->display.pipe_mask))
15551555

1556-
#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1556+
#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != 0)
15571557

15581558
#define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 11)
15591559

‎drivers/gpu/drm/i915/i915_pci.c

Lines changed: 37 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -162,8 +162,8 @@
162162
#define I830_FEATURES \
163163
GEN(2), \
164164
.is_mobile = 1, \
165-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
166-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
165+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
166+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
167167
.display.has_overlay = 1, \
168168
.display.cursor_needs_physical = 1, \
169169
.display.overlay_needs_physical = 1, \
@@ -183,8 +183,8 @@
183183

184184
#define I845_FEATURES \
185185
GEN(2), \
186-
.pipe_mask = BIT(PIPE_A), \
187-
.cpu_transcoder_mask = BIT(TRANSCODER_A), \
186+
.display.pipe_mask = BIT(PIPE_A), \
187+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A), \
188188
.display.has_overlay = 1, \
189189
.display.overlay_needs_physical = 1, \
190190
.display.has_gmch = 1, \
@@ -225,8 +225,8 @@ static const struct intel_device_info i865g_info = {
225225

226226
#define GEN3_FEATURES \
227227
GEN(3), \
228-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
229-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
228+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
229+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
230230
.display.has_gmch = 1, \
231231
.gpu_reset_clobbers_display = true, \
232232
.platform_engine_mask = BIT(RCS0), \
@@ -315,8 +315,8 @@ static const struct intel_device_info pnv_m_info = {
315315

316316
#define GEN4_FEATURES \
317317
GEN(4), \
318-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
319-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
318+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
319+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
320320
.display.has_hotplug = 1, \
321321
.display.has_gmch = 1, \
322322
.gpu_reset_clobbers_display = true, \
@@ -368,8 +368,8 @@ static const struct intel_device_info gm45_info = {
368368

369369
#define GEN5_FEATURES \
370370
GEN(5), \
371-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
372-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
371+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
372+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
373373
.display.has_hotplug = 1, \
374374
.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
375375
.has_snoop = true, \
@@ -398,8 +398,8 @@ static const struct intel_device_info ilk_m_info = {
398398

399399
#define GEN6_FEATURES \
400400
GEN(6), \
401-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
402-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
401+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
402+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
403403
.display.has_hotplug = 1, \
404404
.display.has_fbc = 1, \
405405
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
@@ -449,8 +449,8 @@ static const struct intel_device_info snb_m_gt2_info = {
449449

450450
#define GEN7_FEATURES \
451451
GEN(7), \
452-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
453-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
452+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
453+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
454454
.display.has_hotplug = 1, \
455455
.display.has_fbc = 1, \
456456
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
@@ -504,17 +504,17 @@ static const struct intel_device_info ivb_q_info = {
504504
GEN7_FEATURES,
505505
PLATFORM(INTEL_IVYBRIDGE),
506506
.gt = 2,
507-
.pipe_mask = 0, /* legal, last one wins */
508-
.cpu_transcoder_mask = 0,
507+
.display.pipe_mask = 0, /* legal, last one wins */
508+
.display.cpu_transcoder_mask = 0,
509509
.has_l3_dpf = 1,
510510
};
511511

512512
static const struct intel_device_info vlv_info = {
513513
PLATFORM(INTEL_VALLEYVIEW),
514514
GEN(7),
515515
.is_lp = 1,
516-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
517-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
516+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
517+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
518518
.has_runtime_pm = 1,
519519
.has_rc6 = 1,
520520
.has_reset_engine = true,
@@ -538,7 +538,7 @@ static const struct intel_device_info vlv_info = {
538538
#define G75_FEATURES \
539539
GEN7_FEATURES, \
540540
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
541-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
541+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
542542
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
543543
.display.has_ddi = 1, \
544544
.display.has_fpga_dbg = 1, \
@@ -608,8 +608,8 @@ static const struct intel_device_info bdw_gt3_info = {
608608
static const struct intel_device_info chv_info = {
609609
PLATFORM(INTEL_CHERRYVIEW),
610610
GEN(8),
611-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
612-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
611+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
612+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
613613
.display.has_hotplug = 1,
614614
.is_lp = 1,
615615
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
@@ -686,8 +686,8 @@ static const struct intel_device_info skl_gt4_info = {
686686
.dbuf.slice_mask = BIT(DBUF_S1), \
687687
.display.has_hotplug = 1, \
688688
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
689-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
690-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
689+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
690+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
691691
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
692692
BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
693693
.has_64bit_reloc = 1, \
@@ -795,8 +795,8 @@ static const struct intel_device_info cml_gt2_info = {
795795
#define GEN11_FEATURES \
796796
GEN9_FEATURES, \
797797
GEN11_DEFAULT_PAGE_SIZES, \
798-
.abox_mask = BIT(0), \
799-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
798+
.display.abox_mask = BIT(0), \
799+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
800800
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
801801
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
802802
.pipe_offsets = { \
@@ -847,9 +847,9 @@ static const struct intel_device_info jsl_info = {
847847
#define GEN12_FEATURES \
848848
GEN11_FEATURES, \
849849
GEN(12), \
850-
.abox_mask = GENMASK(2, 1), \
851-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
852-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
850+
.display.abox_mask = GENMASK(2, 1), \
851+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
852+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
853853
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
854854
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
855855
.pipe_offsets = { \
@@ -884,9 +884,9 @@ static const struct intel_device_info tgl_info = {
884884
static const struct intel_device_info rkl_info = {
885885
GEN12_FEATURES,
886886
PLATFORM(INTEL_ROCKETLAKE),
887-
.abox_mask = BIT(0),
888-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
889-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
887+
.display.abox_mask = BIT(0),
888+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
889+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
890890
BIT(TRANSCODER_C),
891891
.display.has_hti = 1,
892892
.display.has_psr_hw_tracking = 0,
@@ -906,7 +906,7 @@ static const struct intel_device_info dg1_info = {
906906
DGFX_FEATURES,
907907
.graphics_rel = 10,
908908
PLATFORM(INTEL_DG1),
909-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
909+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
910910
.require_force_probe = 1,
911911
.platform_engine_mask =
912912
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
@@ -918,7 +918,7 @@ static const struct intel_device_info dg1_info = {
918918
static const struct intel_device_info adl_s_info = {
919919
GEN12_FEATURES,
920920
PLATFORM(INTEL_ALDERLAKE_S),
921-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
921+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
922922
.display.has_hti = 1,
923923
.display.has_psr_hw_tracking = 0,
924924
.platform_engine_mask =
@@ -935,7 +935,7 @@ static const struct intel_device_info adl_s_info = {
935935
}
936936

937937
#define XE_LPD_FEATURES \
938-
.abox_mask = GENMASK(1, 0), \
938+
.display.abox_mask = GENMASK(1, 0), \
939939
.color = { .degamma_lut_size = 128, .gamma_lut_size = 1024, \
940940
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
941941
DRM_COLOR_LUT_EQUAL_CHANNELS, \
@@ -955,7 +955,7 @@ static const struct intel_device_info adl_s_info = {
955955
.display.has_ipc = 1, \
956956
.display.has_psr = 1, \
957957
.display.ver = 13, \
958-
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
958+
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
959959
.pipe_offsets = { \
960960
[TRANSCODER_A] = PIPE_A_OFFSET, \
961961
[TRANSCODER_B] = PIPE_B_OFFSET, \
@@ -978,7 +978,7 @@ static const struct intel_device_info adl_p_info = {
978978
GEN12_FEATURES,
979979
XE_LPD_FEATURES,
980980
PLATFORM(INTEL_ALDERLAKE_P),
981-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
981+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
982982
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
983983
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
984984
.display.has_cdclk_crawl = 1,
@@ -1027,7 +1027,6 @@ static const struct intel_device_info xehpsdv_info = {
10271027
DGFX_FEATURES,
10281028
PLATFORM(INTEL_XEHPSDV),
10291029
.display = { },
1030-
.pipe_mask = 0,
10311030
.platform_engine_mask =
10321031
BIT(RCS0) | BIT(BCS0) |
10331032
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1050,7 +1049,7 @@ static const struct intel_device_info dg2_info = {
10501049
BIT(VECS0) | BIT(VECS1) |
10511050
BIT(VCS0) | BIT(VCS2),
10521051
.require_force_probe = 1,
1053-
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1052+
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
10541053
BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
10551054
};
10561055

‎drivers/gpu/drm/i915/intel_device_info.c

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -333,33 +333,33 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
333333
!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
334334
drm_info(&dev_priv->drm,
335335
"Display fused off, disabling\n");
336-
info->pipe_mask = 0;
337-
info->cpu_transcoder_mask = 0;
336+
info->display.pipe_mask = 0;
337+
info->display.cpu_transcoder_mask = 0;
338338
} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
339339
drm_info(&dev_priv->drm, "PipeC fused off\n");
340-
info->pipe_mask &= ~BIT(PIPE_C);
341-
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
340+
info->display.pipe_mask &= ~BIT(PIPE_C);
341+
info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
342342
}
343343
} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
344344
u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
345345

346346
if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
347-
info->pipe_mask &= ~BIT(PIPE_A);
348-
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
347+
info->display.pipe_mask &= ~BIT(PIPE_A);
348+
info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
349349
}
350350
if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
351-
info->pipe_mask &= ~BIT(PIPE_B);
352-
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
351+
info->display.pipe_mask &= ~BIT(PIPE_B);
352+
info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
353353
}
354354
if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
355-
info->pipe_mask &= ~BIT(PIPE_C);
356-
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
355+
info->display.pipe_mask &= ~BIT(PIPE_C);
356+
info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
357357
}
358358

359359
if (DISPLAY_VER(dev_priv) >= 12 &&
360360
(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
361-
info->pipe_mask &= ~BIT(PIPE_D);
362-
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
361+
info->display.pipe_mask &= ~BIT(PIPE_D);
362+
info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
363363
}
364364

365365
if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)

‎drivers/gpu/drm/i915/intel_device_info.h

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -192,18 +192,17 @@ struct intel_device_info {
192192

193193
u8 gt; /* GT number, 0 if undefined */
194194

195-
u8 pipe_mask;
196-
u8 cpu_transcoder_mask;
197-
198-
u8 abox_mask;
199-
200195
#define DEFINE_FLAG(name) u8 name:1
201196
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
202197
#undef DEFINE_FLAG
203198

204199
struct {
205200
u8 ver;
206201

202+
u8 pipe_mask;
203+
u8 cpu_transcoder_mask;
204+
u8 abox_mask;
205+
207206
#define DEFINE_FLAG(name) u8 name:1
208207
DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
209208
#undef DEFINE_FLAG

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