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Evan Quanalexdeucher
Evan Quan
authored and
alexdeucher
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drm/amd/powerplay: move SMC message issuing APIs to smu_cmn.c
Considering they can be shared by all ASICs. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
1 parent c1b353b commit 66c8682

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13 files changed

+252
-313
lines changed

13 files changed

+252
-313
lines changed

‎drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -46,19 +46,6 @@
4646
#undef pr_info
4747
#undef pr_debug
4848

49-
#undef __SMU_DUMMY_MAP
50-
#define __SMU_DUMMY_MAP(type) #type
51-
static const char* __smu_message_names[] = {
52-
SMU_MESSAGE_TYPES
53-
};
54-
55-
const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
56-
{
57-
if (type < 0 || type >= SMU_MSG_MAX_COUNT)
58-
return "unknown smu message";
59-
return __smu_message_names[type];
60-
}
61-
6249
size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
6350
{
6451
size_t size = 0;

‎drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

Lines changed: 13 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -455,13 +455,13 @@ static int arcturus_run_btc(struct smu_context *smu)
455455
{
456456
int ret = 0;
457457

458-
ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
458+
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
459459
if (ret) {
460460
dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
461461
return ret;
462462
}
463463

464-
return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
464+
return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
465465
}
466466

467467
static int arcturus_populate_umd_state_clk(struct smu_context *smu)
@@ -839,7 +839,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu,
839839
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
840840
(feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
841841
freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
842-
ret = smu_send_smc_msg_with_param(smu,
842+
ret = smu_cmn_send_smc_msg_with_param(smu,
843843
(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
844844
(PPCLK_GFXCLK << 16) | (freq & 0xffff),
845845
NULL);
@@ -853,7 +853,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu,
853853
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
854854
(feature_mask & FEATURE_DPM_UCLK_MASK)) {
855855
freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
856-
ret = smu_send_smc_msg_with_param(smu,
856+
ret = smu_cmn_send_smc_msg_with_param(smu,
857857
(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
858858
(PPCLK_UCLK << 16) | (freq & 0xffff),
859859
NULL);
@@ -867,7 +867,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu,
867867
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
868868
(feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
869869
freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
870-
ret = smu_send_smc_msg_with_param(smu,
870+
ret = smu_cmn_send_smc_msg_with_param(smu,
871871
(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
872872
(PPCLK_SOCCLK << 16) | (freq & 0xffff),
873873
NULL);
@@ -1358,7 +1358,7 @@ static int arcturus_set_power_profile_mode(struct smu_context *smu,
13581358
return -EINVAL;
13591359
}
13601360

1361-
ret = smu_send_smc_msg_with_param(smu,
1361+
ret = smu_cmn_send_smc_msg_with_param(smu,
13621362
SMU_MSG_SetWorkloadMask,
13631363
1 << workload_type,
13641364
NULL);
@@ -2134,8 +2134,8 @@ static void arcturus_get_unique_id(struct smu_context *smu)
21342134
}
21352135

21362136
/* Get the SN to turn into a Unique ID */
2137-
smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2138-
smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2137+
smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2138+
smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
21392139

21402140
id = ((uint64_t)bottom32 << 32) | top32;
21412141
adev->unique_id = id;
@@ -2175,7 +2175,7 @@ static int arcturus_set_df_cstate(struct smu_context *smu,
21752175
return -EINVAL;
21762176
}
21772177

2178-
return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2178+
return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
21792179
}
21802180

21812181
static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
@@ -2196,12 +2196,12 @@ static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
21962196
}
21972197

21982198
if (en)
2199-
return smu_send_smc_msg_with_param(smu,
2199+
return smu_cmn_send_smc_msg_with_param(smu,
22002200
SMU_MSG_GmiPwrDnControl,
22012201
1,
22022202
NULL);
22032203

2204-
return smu_send_smc_msg_with_param(smu,
2204+
return smu_cmn_send_smc_msg_with_param(smu,
22052205
SMU_MSG_GmiPwrDnControl,
22062206
0,
22072207
NULL);
@@ -2294,7 +2294,8 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
22942294
.set_tool_table_location = smu_v11_0_set_tool_table_location,
22952295
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
22962296
.system_features_control = smu_v11_0_system_features_control,
2297-
.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2297+
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2298+
.send_smc_msg = smu_cmn_send_smc_msg,
22982299
.init_display_count = NULL,
22992300
.set_allowed_mask = smu_v11_0_set_allowed_mask,
23002301
.get_enabled_mask = smu_cmn_get_enabled_mask,

‎drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -528,6 +528,9 @@ struct pptable_funcs {
528528
int (*system_features_control)(struct smu_context *smu, bool en);
529529
int (*send_smc_msg_with_param)(struct smu_context *smu,
530530
enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
531+
int (*send_smc_msg)(struct smu_context *smu,
532+
enum smu_message_type msg,
533+
uint32_t *read_arg);
531534
int (*init_display_count)(struct smu_context *smu, uint32_t count);
532535
int (*set_allowed_mask)(struct smu_context *smu);
533536
int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
@@ -763,7 +766,6 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
763766
int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
764767
int smu_set_display_count(struct smu_context *smu, uint32_t count);
765768
int smu_set_ac_dc(struct smu_context *smu);
766-
const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
767769
size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
768770
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
769771
int smu_force_clk_levels(struct smu_context *smu,

‎drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -165,12 +165,6 @@ int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
165165
int smu_v11_0_system_features_control(struct smu_context *smu,
166166
bool en);
167167

168-
int
169-
smu_v11_0_send_msg_with_param(struct smu_context *smu,
170-
enum smu_message_type msg,
171-
uint32_t param,
172-
uint32_t *read_arg);
173-
174168
int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
175169

176170
int smu_v11_0_set_allowed_mask(struct smu_context *smu);

‎drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -31,17 +31,6 @@
3131
#define MP1_Public 0x03b00000
3232
#define MP1_SRAM 0x03c00004
3333

34-
int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
35-
uint16_t msg);
36-
37-
int smu_v12_0_wait_for_response(struct smu_context *smu);
38-
39-
int
40-
smu_v12_0_send_msg_with_param(struct smu_context *smu,
41-
enum smu_message_type msg,
42-
uint32_t param,
43-
uint32_t *read_arg);
44-
4534
int smu_v12_0_check_fw_status(struct smu_context *smu);
4635

4736
int smu_v12_0_check_fw_version(struct smu_context *smu);

‎drivers/gpu/drm/amd/powerplay/navi10_ppt.c

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -786,14 +786,14 @@ static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
786786
if (enable) {
787787
/* vcn dpm on is a prerequisite for vcn power gate messages */
788788
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
789-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
789+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
790790
if (ret)
791791
return ret;
792792
}
793793
power_gate->vcn_gated = false;
794794
} else {
795795
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
796-
ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
796+
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
797797
if (ret)
798798
return ret;
799799
}
@@ -811,14 +811,14 @@ static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
811811

812812
if (enable) {
813813
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
814-
ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
814+
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
815815
if (ret)
816816
return ret;
817817
}
818818
power_gate->jpeg_gated = false;
819819
} else {
820820
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
821-
ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
821+
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
822822
if (ret)
823823
return ret;
824824
}
@@ -1258,7 +1258,7 @@ static int navi10_pre_display_config_changed(struct smu_context *smu)
12581258
int ret = 0;
12591259
uint32_t max_freq = 0;
12601260

1261-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1261+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
12621262
if (ret)
12631263
return ret;
12641264

@@ -1281,7 +1281,7 @@ static int navi10_display_config_changed(struct smu_context *smu)
12811281
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
12821282
smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
12831283
smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1284-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1284+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
12851285
smu->display_config->num_display,
12861286
NULL);
12871287
if (ret)
@@ -1541,7 +1541,7 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
15411541
smu->power_profile_mode);
15421542
if (workload_type < 0)
15431543
return -EINVAL;
1544-
smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1544+
smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
15451545
1 << workload_type, NULL);
15461546

15471547
return ret;
@@ -1564,7 +1564,7 @@ static int navi10_notify_smc_display_config(struct smu_context *smu)
15641564
ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
15651565
if (!ret) {
15661566
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1567-
ret = smu_send_smc_msg_with_param(smu,
1567+
ret = smu_cmn_send_smc_msg_with_param(smu,
15681568
SMU_MSG_SetMinDeepSleepDcefclk,
15691569
min_clocks.dcef_clock_in_sr/100,
15701570
NULL);
@@ -1884,7 +1884,7 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
18841884
((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
18851885
(pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
18861886
pptable->PcieLaneCount[i] : pcie_width_cap);
1887-
ret = smu_send_smc_msg_with_param(smu,
1887+
ret = smu_cmn_send_smc_msg_with_param(smu,
18881888
SMU_MSG_OverridePcieParameters,
18891889
smu_pcie_arg,
18901890
NULL);
@@ -1936,7 +1936,7 @@ static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
19361936
uint32_t value = 0;
19371937
int ret;
19381938

1939-
ret = smu_send_smc_msg_with_param(smu,
1939+
ret = smu_cmn_send_smc_msg_with_param(smu,
19401940
SMU_MSG_GetVoltageByDpm,
19411941
param,
19421942
&value);
@@ -2184,7 +2184,7 @@ static int navi10_run_btc(struct smu_context *smu)
21842184
{
21852185
int ret = 0;
21862186

2187-
ret = smu_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2187+
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
21882188
if (ret)
21892189
dev_err(smu->adev->dev, "RunBtc failed!\n");
21902190

@@ -2196,9 +2196,9 @@ static int navi10_dummy_pstate_control(struct smu_context *smu, bool enable)
21962196
int result = 0;
21972197

21982198
if (!enable)
2199-
result = smu_send_smc_msg(smu, SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE, NULL);
2199+
result = smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE, NULL);
22002200
else
2201-
result = smu_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2201+
result = smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
22022202

22032203
return result;
22042204
}
@@ -2305,7 +2305,8 @@ static const struct pptable_funcs navi10_ppt_funcs = {
23052305
.set_tool_table_location = smu_v11_0_set_tool_table_location,
23062306
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
23072307
.system_features_control = smu_v11_0_system_features_control,
2308-
.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2308+
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2309+
.send_smc_msg = smu_cmn_send_smc_msg,
23092310
.init_display_count = smu_v11_0_init_display_count,
23102311
.set_allowed_mask = smu_v11_0_set_allowed_mask,
23112312
.get_enabled_mask = smu_cmn_get_enabled_mask,

‎drivers/gpu/drm/amd/powerplay/renoir_ppt.c

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -295,7 +295,7 @@ static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
295295
switch (clk_type) {
296296
case SMU_GFXCLK:
297297
case SMU_SCLK:
298-
ret = smu_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
298+
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
299299
if (ret) {
300300
dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
301301
goto failed;
@@ -323,7 +323,7 @@ static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
323323
switch (clk_type) {
324324
case SMU_GFXCLK:
325325
case SMU_SCLK:
326-
ret = smu_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
326+
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
327327
if (ret) {
328328
dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
329329
goto failed;
@@ -465,14 +465,14 @@ static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
465465
if (enable) {
466466
/* vcn dpm on is a prerequisite for vcn power gate messages */
467467
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
468-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
468+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
469469
if (ret)
470470
return ret;
471471
}
472472
power_gate->vcn_gated = false;
473473
} else {
474474
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
475-
ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
475+
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
476476
if (ret)
477477
return ret;
478478
}
@@ -490,14 +490,14 @@ static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
490490

491491
if (enable) {
492492
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
493-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
493+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
494494
if (ret)
495495
return ret;
496496
}
497497
power_gate->jpeg_gated = false;
498498
} else {
499499
if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
500-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
500+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
501501
if (ret)
502502
return ret;
503503
}
@@ -688,13 +688,13 @@ static int renoir_force_clk_levels(struct smu_context *smu,
688688
ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
689689
if (ret)
690690
return ret;
691-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
691+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
692692
soft_max_level == 0 ? min_freq :
693693
soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq,
694694
NULL);
695695
if (ret)
696696
return ret;
697-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
697+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
698698
soft_min_level == 2 ? max_freq :
699699
soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq,
700700
NULL);
@@ -708,10 +708,10 @@ static int renoir_force_clk_levels(struct smu_context *smu,
708708
ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
709709
if (ret)
710710
return ret;
711-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
711+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
712712
if (ret)
713713
return ret;
714-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
714+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
715715
if (ret)
716716
return ret;
717717
break;
@@ -723,10 +723,10 @@ static int renoir_force_clk_levels(struct smu_context *smu,
723723
ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
724724
if (ret)
725725
return ret;
726-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
726+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
727727
if (ret)
728728
return ret;
729-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
729+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
730730
if (ret)
731731
return ret;
732732
break;
@@ -760,7 +760,7 @@ static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, u
760760
return -EINVAL;
761761
}
762762

763-
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
763+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
764764
1 << workload_type,
765765
NULL);
766766
if (ret) {
@@ -1010,7 +1010,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
10101010
.check_fw_status = smu_v12_0_check_fw_status,
10111011
.check_fw_version = smu_v12_0_check_fw_version,
10121012
.powergate_sdma = smu_v12_0_powergate_sdma,
1013-
.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
1013+
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1014+
.send_smc_msg = smu_cmn_send_smc_msg,
10141015
.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
10151016
.gfx_off_control = smu_v12_0_gfx_off_control,
10161017
.get_gfx_off_status = smu_v12_0_get_gfxoff_status,

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