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#include <asm/fpu/api.h>
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#include <asm/asm.h>
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+ /*
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+ * Use KFPU_387. MMX instructions are not affected by MXCSR,
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+ * but both AMD and Intel documentation states that even integer MMX
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+ * operations will result in #MF if an exception is pending in FCW.
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+ *
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+ * EMMS is not needed afterwards because, after calling kernel_fpu_end(),
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+ * any subsequent user of the 387 stack will reinitialize it using
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+ * KFPU_387.
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+ */
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+
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void * _mmx_memcpy (void * to , const void * from , size_t len )
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{
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void * p ;
@@ -37,7 +47,7 @@ void *_mmx_memcpy(void *to, const void *from, size_t len)
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p = to ;
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i = len >> 6 ; /* len/64 */
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- kernel_fpu_begin ( );
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+ kernel_fpu_begin_mask ( KFPU_387 );
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__asm__ __volatile__ (
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"1: prefetch (%0)\n" /* This set is 28 bytes */
@@ -127,7 +137,7 @@ static void fast_clear_page(void *page)
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{
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int i ;
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- kernel_fpu_begin ( );
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+ kernel_fpu_begin_mask ( KFPU_387 );
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__asm__ __volatile__ (
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" pxor %%mm0, %%mm0\n" : :
@@ -160,7 +170,7 @@ static void fast_copy_page(void *to, void *from)
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{
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int i ;
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- kernel_fpu_begin ( );
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+ kernel_fpu_begin_mask ( KFPU_387 );
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/*
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* maybe the prefetch stuff can go before the expensive fnsave...
@@ -247,7 +257,7 @@ static void fast_clear_page(void *page)
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{
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int i ;
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- kernel_fpu_begin ( );
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+ kernel_fpu_begin_mask ( KFPU_387 );
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__asm__ __volatile__ (
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" pxor %%mm0, %%mm0\n" : :
@@ -282,7 +292,7 @@ static void fast_copy_page(void *to, void *from)
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{
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int i ;
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- kernel_fpu_begin ( );
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+ kernel_fpu_begin_mask ( KFPU_387 );
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__asm__ __volatile__ (
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"1: prefetch (%0)\n"
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