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Sean Andersonvinodkoul
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phy: zynqmp: Store instance instead of type
The phy "type" is just the combination of protocol and instance, and is never used apart from that. Store the instance directly, instead of converting to a type first. No functional change intended. Signed-off-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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drivers/phy/xilinx/phy-zynqmp.c

Lines changed: 31 additions & 84 deletions
Original file line numberDiff line numberDiff line change
@@ -147,22 +147,6 @@
147147
/* Total number of controllers */
148148
#define CONTROLLERS_PER_LANE 5
149149

150-
/* Protocol Type parameters */
151-
#define XPSGTR_TYPE_USB0 0 /* USB controller 0 */
152-
#define XPSGTR_TYPE_USB1 1 /* USB controller 1 */
153-
#define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
154-
#define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */
155-
#define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */
156-
#define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */
157-
#define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */
158-
#define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */
159-
#define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */
160-
#define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */
161-
#define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */
162-
#define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */
163-
#define XPSGTR_TYPE_SGMII2 12 /* Ethernet SGMII controller 2 */
164-
#define XPSGTR_TYPE_SGMII3 13 /* Ethernet SGMII controller 3 */
165-
166150
/* Timeout values */
167151
#define TIMEOUT_US 1000
168152

@@ -185,7 +169,8 @@ struct xpsgtr_ssc {
185169
/**
186170
* struct xpsgtr_phy - representation of a lane
187171
* @phy: pointer to the kernel PHY device
188-
* @type: controller which uses this lane
172+
* @instance: instance of the protocol type (such as the lane within a
173+
* protocol, or the USB/Ethernet controller)
189174
* @lane: lane number
190175
* @protocol: protocol in which the lane operates
191176
* @skip_phy_init: skip phy_init() if true
@@ -194,7 +179,7 @@ struct xpsgtr_ssc {
194179
*/
195180
struct xpsgtr_phy {
196181
struct phy *phy;
197-
u8 type;
182+
u8 instance;
198183
u8 lane;
199184
u8 protocol;
200185
bool skip_phy_init;
@@ -331,8 +316,8 @@ static int xpsgtr_wait_pll_lock(struct phy *phy)
331316

332317
if (ret == -ETIMEDOUT)
333318
dev_err(gtr_dev->dev,
334-
"lane %u (type %u, protocol %u): PLL lock timeout\n",
335-
gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);
319+
"lane %u (protocol %u, instance %u): PLL lock timeout\n",
320+
gtr_phy->lane, gtr_phy->protocol, gtr_phy->instance);
336321

337322
return ret;
338323
}
@@ -645,8 +630,7 @@ static int xpsgtr_phy_power_on(struct phy *phy)
645630
* cumulating waits for both lanes. The user is expected to initialize
646631
* lane 0 last.
647632
*/
648-
if (gtr_phy->protocol != ICM_PROTOCOL_DP ||
649-
gtr_phy->type == XPSGTR_TYPE_DP_0)
633+
if (gtr_phy->protocol != ICM_PROTOCOL_DP || !gtr_phy->instance)
650634
ret = xpsgtr_wait_pll_lock(phy);
651635

652636
return ret;
@@ -676,96 +660,59 @@ static const struct phy_ops xpsgtr_phyops = {
676660
* OF Xlate Support
677661
*/
678662

679-
/* Set the lane type and protocol based on the PHY type and instance number. */
663+
/* Set the lane protocol and instance based on the PHY type and instance number. */
680664
static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
681665
unsigned int phy_instance)
682666
{
683667
unsigned int num_phy_types;
684-
const int *phy_types;
685668

686669
switch (phy_type) {
687-
case PHY_TYPE_SATA: {
688-
static const int types[] = {
689-
XPSGTR_TYPE_SATA_0,
690-
XPSGTR_TYPE_SATA_1,
691-
};
692-
693-
phy_types = types;
694-
num_phy_types = ARRAY_SIZE(types);
670+
case PHY_TYPE_SATA:
671+
num_phy_types = 2;
695672
gtr_phy->protocol = ICM_PROTOCOL_SATA;
696673
break;
697-
}
698-
case PHY_TYPE_USB3: {
699-
static const int types[] = {
700-
XPSGTR_TYPE_USB0,
701-
XPSGTR_TYPE_USB1,
702-
};
703-
704-
phy_types = types;
705-
num_phy_types = ARRAY_SIZE(types);
674+
case PHY_TYPE_USB3:
675+
num_phy_types = 2;
706676
gtr_phy->protocol = ICM_PROTOCOL_USB;
707677
break;
708-
}
709-
case PHY_TYPE_DP: {
710-
static const int types[] = {
711-
XPSGTR_TYPE_DP_0,
712-
XPSGTR_TYPE_DP_1,
713-
};
714-
715-
phy_types = types;
716-
num_phy_types = ARRAY_SIZE(types);
678+
case PHY_TYPE_DP:
679+
num_phy_types = 2;
717680
gtr_phy->protocol = ICM_PROTOCOL_DP;
718681
break;
719-
}
720-
case PHY_TYPE_PCIE: {
721-
static const int types[] = {
722-
XPSGTR_TYPE_PCIE_0,
723-
XPSGTR_TYPE_PCIE_1,
724-
XPSGTR_TYPE_PCIE_2,
725-
XPSGTR_TYPE_PCIE_3,
726-
};
727-
728-
phy_types = types;
729-
num_phy_types = ARRAY_SIZE(types);
682+
case PHY_TYPE_PCIE:
683+
num_phy_types = 4;
730684
gtr_phy->protocol = ICM_PROTOCOL_PCIE;
731685
break;
732-
}
733-
case PHY_TYPE_SGMII: {
734-
static const int types[] = {
735-
XPSGTR_TYPE_SGMII0,
736-
XPSGTR_TYPE_SGMII1,
737-
XPSGTR_TYPE_SGMII2,
738-
XPSGTR_TYPE_SGMII3,
739-
};
740-
741-
phy_types = types;
742-
num_phy_types = ARRAY_SIZE(types);
686+
case PHY_TYPE_SGMII:
687+
num_phy_types = 4;
743688
gtr_phy->protocol = ICM_PROTOCOL_SGMII;
744689
break;
745-
}
746690
default:
747691
return -EINVAL;
748692
}
749693

750694
if (phy_instance >= num_phy_types)
751695
return -EINVAL;
752696

753-
gtr_phy->type = phy_types[phy_instance];
697+
gtr_phy->instance = phy_instance;
754698
return 0;
755699
}
756700

757701
/*
758-
* Valid combinations of controllers and lanes (Interconnect Matrix).
702+
* Valid combinations of controllers and lanes (Interconnect Matrix). Each
703+
* "instance" represents one controller for a lane. For PCIe and DP, the
704+
* "instance" is the logical lane in the link. For SATA, USB, and SGMII,
705+
* the instance is the index of the controller.
706+
*
707+
* This information is only used to validate the devicetree reference, and is
708+
* not used when programming the hardware.
759709
*/
760710
static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
761-
{ XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
762-
XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 },
763-
{ XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0,
764-
XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 },
765-
{ XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
766-
XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 },
767-
{ XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1,
768-
XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 }
711+
/* PCIe, SATA, USB, DP, SGMII */
712+
{ 0, 0, 0, 1, 0 }, /* Lane 0 */
713+
{ 1, 1, 0, 0, 1 }, /* Lane 1 */
714+
{ 2, 0, 0, 1, 2 }, /* Lane 2 */
715+
{ 3, 1, 1, 0, 3 }, /* Lane 3 */
769716
};
770717

771718
/* Translate OF phandle and args to PHY instance. */
@@ -820,7 +767,7 @@ static struct phy *xpsgtr_xlate(struct device *dev,
820767
* is allowed to operate on the lane.
821768
*/
822769
for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
823-
if (icm_matrix[phy_lane][i] == gtr_phy->type)
770+
if (icm_matrix[phy_lane][i] == gtr_phy->instance)
824771
return gtr_phy->phy;
825772
}
826773

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