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Steven Liulinusw
Steven Liu
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linusw
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pinctrl: rockchip: Add rk3576 pinctrl support
Add support for the 5 rk3576 GPIO banks. Signed-off-by: Steven Liu <[email protected]> Signed-off-by: Detlev Casanova <[email protected]> Acked-by: Dragan Simic <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Linus Walleij <[email protected]>
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‎drivers/pinctrl/pinctrl-rockchip.c

Lines changed: 207 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,27 @@
8484
}, \
8585
}
8686

87+
#define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, \
88+
iom1, iom2, iom3, \
89+
offset0, offset1, \
90+
offset2, offset3, pull0, \
91+
pull1, pull2, pull3) \
92+
{ \
93+
.bank_num = id, \
94+
.nr_pins = pins, \
95+
.name = label, \
96+
.iomux = { \
97+
{ .type = iom0, .offset = offset0 }, \
98+
{ .type = iom1, .offset = offset1 }, \
99+
{ .type = iom2, .offset = offset2 }, \
100+
{ .type = iom3, .offset = offset3 }, \
101+
}, \
102+
.pull_type[0] = pull0, \
103+
.pull_type[1] = pull1, \
104+
.pull_type[2] = pull2, \
105+
.pull_type[3] = pull3, \
106+
}
107+
87108
#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
88109
{ \
89110
.bank_num = id, \
@@ -1120,6 +1141,11 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
11201141
if (bank->recalced_mask & BIT(pin))
11211142
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
11221143

1144+
if (ctrl->type == RK3576) {
1145+
if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1146+
reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1147+
}
1148+
11231149
if (ctrl->type == RK3588) {
11241150
if (bank->bank_num == 0) {
11251151
if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
@@ -1234,6 +1260,11 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
12341260
if (bank->recalced_mask & BIT(pin))
12351261
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
12361262

1263+
if (ctrl->type == RK3576) {
1264+
if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1265+
reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1266+
}
1267+
12371268
if (ctrl->type == RK3588) {
12381269
if (bank->bank_num == 0) {
12391270
if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
@@ -2038,6 +2069,142 @@ static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
20382069
return 0;
20392070
}
20402071

2072+
#define RK3576_DRV_BITS_PER_PIN 4
2073+
#define RK3576_DRV_PINS_PER_REG 4
2074+
#define RK3576_DRV_GPIO0_AL_OFFSET 0x10
2075+
#define RK3576_DRV_GPIO0_BH_OFFSET 0x2014
2076+
#define RK3576_DRV_GPIO1_OFFSET 0x6020
2077+
#define RK3576_DRV_GPIO2_OFFSET 0x6040
2078+
#define RK3576_DRV_GPIO3_OFFSET 0x6060
2079+
#define RK3576_DRV_GPIO4_AL_OFFSET 0x6080
2080+
#define RK3576_DRV_GPIO4_CL_OFFSET 0xA090
2081+
#define RK3576_DRV_GPIO4_DL_OFFSET 0xB098
2082+
2083+
static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2084+
int pin_num, struct regmap **regmap,
2085+
int *reg, u8 *bit)
2086+
{
2087+
struct rockchip_pinctrl *info = bank->drvdata;
2088+
2089+
*regmap = info->regmap_base;
2090+
2091+
if (bank->bank_num == 0 && pin_num < 12)
2092+
*reg = RK3576_DRV_GPIO0_AL_OFFSET;
2093+
else if (bank->bank_num == 0)
2094+
*reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
2095+
else if (bank->bank_num == 1)
2096+
*reg = RK3576_DRV_GPIO1_OFFSET;
2097+
else if (bank->bank_num == 2)
2098+
*reg = RK3576_DRV_GPIO2_OFFSET;
2099+
else if (bank->bank_num == 3)
2100+
*reg = RK3576_DRV_GPIO3_OFFSET;
2101+
else if (bank->bank_num == 4 && pin_num < 16)
2102+
*reg = RK3576_DRV_GPIO4_AL_OFFSET;
2103+
else if (bank->bank_num == 4 && pin_num < 24)
2104+
*reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
2105+
else if (bank->bank_num == 4)
2106+
*reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
2107+
else
2108+
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2109+
2110+
*reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
2111+
*bit = pin_num % RK3576_DRV_PINS_PER_REG;
2112+
*bit *= RK3576_DRV_BITS_PER_PIN;
2113+
2114+
return 0;
2115+
}
2116+
2117+
#define RK3576_PULL_BITS_PER_PIN 2
2118+
#define RK3576_PULL_PINS_PER_REG 8
2119+
#define RK3576_PULL_GPIO0_AL_OFFSET 0x20
2120+
#define RK3576_PULL_GPIO0_BH_OFFSET 0x2028
2121+
#define RK3576_PULL_GPIO1_OFFSET 0x6110
2122+
#define RK3576_PULL_GPIO2_OFFSET 0x6120
2123+
#define RK3576_PULL_GPIO3_OFFSET 0x6130
2124+
#define RK3576_PULL_GPIO4_AL_OFFSET 0x6140
2125+
#define RK3576_PULL_GPIO4_CL_OFFSET 0xA148
2126+
#define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C
2127+
2128+
static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2129+
int pin_num, struct regmap **regmap,
2130+
int *reg, u8 *bit)
2131+
{
2132+
struct rockchip_pinctrl *info = bank->drvdata;
2133+
2134+
*regmap = info->regmap_base;
2135+
2136+
if (bank->bank_num == 0 && pin_num < 12)
2137+
*reg = RK3576_PULL_GPIO0_AL_OFFSET;
2138+
else if (bank->bank_num == 0)
2139+
*reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
2140+
else if (bank->bank_num == 1)
2141+
*reg = RK3576_PULL_GPIO1_OFFSET;
2142+
else if (bank->bank_num == 2)
2143+
*reg = RK3576_PULL_GPIO2_OFFSET;
2144+
else if (bank->bank_num == 3)
2145+
*reg = RK3576_PULL_GPIO3_OFFSET;
2146+
else if (bank->bank_num == 4 && pin_num < 16)
2147+
*reg = RK3576_PULL_GPIO4_AL_OFFSET;
2148+
else if (bank->bank_num == 4 && pin_num < 24)
2149+
*reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
2150+
else if (bank->bank_num == 4)
2151+
*reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
2152+
else
2153+
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2154+
2155+
*reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
2156+
*bit = pin_num % RK3576_PULL_PINS_PER_REG;
2157+
*bit *= RK3576_PULL_BITS_PER_PIN;
2158+
2159+
return 0;
2160+
}
2161+
2162+
#define RK3576_SMT_BITS_PER_PIN 1
2163+
#define RK3576_SMT_PINS_PER_REG 8
2164+
#define RK3576_SMT_GPIO0_AL_OFFSET 0x30
2165+
#define RK3576_SMT_GPIO0_BH_OFFSET 0x2040
2166+
#define RK3576_SMT_GPIO1_OFFSET 0x6210
2167+
#define RK3576_SMT_GPIO2_OFFSET 0x6220
2168+
#define RK3576_SMT_GPIO3_OFFSET 0x6230
2169+
#define RK3576_SMT_GPIO4_AL_OFFSET 0x6240
2170+
#define RK3576_SMT_GPIO4_CL_OFFSET 0xA248
2171+
#define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C
2172+
2173+
static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2174+
int pin_num,
2175+
struct regmap **regmap,
2176+
int *reg, u8 *bit)
2177+
{
2178+
struct rockchip_pinctrl *info = bank->drvdata;
2179+
2180+
*regmap = info->regmap_base;
2181+
2182+
if (bank->bank_num == 0 && pin_num < 12)
2183+
*reg = RK3576_SMT_GPIO0_AL_OFFSET;
2184+
else if (bank->bank_num == 0)
2185+
*reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
2186+
else if (bank->bank_num == 1)
2187+
*reg = RK3576_SMT_GPIO1_OFFSET;
2188+
else if (bank->bank_num == 2)
2189+
*reg = RK3576_SMT_GPIO2_OFFSET;
2190+
else if (bank->bank_num == 3)
2191+
*reg = RK3576_SMT_GPIO3_OFFSET;
2192+
else if (bank->bank_num == 4 && pin_num < 16)
2193+
*reg = RK3576_SMT_GPIO4_AL_OFFSET;
2194+
else if (bank->bank_num == 4 && pin_num < 24)
2195+
*reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
2196+
else if (bank->bank_num == 4)
2197+
*reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
2198+
else
2199+
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2200+
2201+
*reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
2202+
*bit = pin_num % RK3576_SMT_PINS_PER_REG;
2203+
*bit *= RK3576_SMT_BITS_PER_PIN;
2204+
2205+
return 0;
2206+
}
2207+
20412208
#define RK3588_PMU1_IOC_REG (0x0000)
20422209
#define RK3588_PMU2_IOC_REG (0x4000)
20432210
#define RK3588_BUS_IOC_REG (0x8000)
@@ -2332,6 +2499,10 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
23322499
rmask_bits = RK3568_DRV_BITS_PER_PIN;
23332500
ret = (1 << (strength + 1)) - 1;
23342501
goto config;
2502+
} else if (ctrl->type == RK3576) {
2503+
rmask_bits = RK3576_DRV_BITS_PER_PIN;
2504+
ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
2505+
goto config;
23352506
}
23362507

23372508
if (ctrl->type == RV1126) {
@@ -2469,6 +2640,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
24692640
case RK3368:
24702641
case RK3399:
24712642
case RK3568:
2643+
case RK3576:
24722644
case RK3588:
24732645
pull_type = bank->pull_type[pin_num / 8];
24742646
data >>= bit;
@@ -2528,6 +2700,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
25282700
case RK3368:
25292701
case RK3399:
25302702
case RK3568:
2703+
case RK3576:
25312704
case RK3588:
25322705
pull_type = bank->pull_type[pin_num / 8];
25332706
ret = -EINVAL;
@@ -2793,6 +2966,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
27932966
case RK3368:
27942967
case RK3399:
27952968
case RK3568:
2969+
case RK3576:
27962970
case RK3588:
27972971
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
27982972
}
@@ -3949,6 +4123,37 @@ static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
39494123
.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
39504124
};
39514125

4126+
#define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \
4127+
PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \
4128+
IOMUX_WIDTH_4BIT, \
4129+
IOMUX_WIDTH_4BIT, \
4130+
IOMUX_WIDTH_4BIT, \
4131+
IOMUX_WIDTH_4BIT, \
4132+
OFFSET0, OFFSET1, \
4133+
OFFSET2, OFFSET3, \
4134+
PULL_TYPE_IO_1V8_ONLY, \
4135+
PULL_TYPE_IO_1V8_ONLY, \
4136+
PULL_TYPE_IO_1V8_ONLY, \
4137+
PULL_TYPE_IO_1V8_ONLY)
4138+
4139+
static struct rockchip_pin_bank rk3576_pin_banks[] = {
4140+
RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C),
4141+
RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038),
4142+
RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058),
4143+
RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078),
4144+
RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398),
4145+
};
4146+
4147+
static struct rockchip_pin_ctrl rk3576_pin_ctrl __maybe_unused = {
4148+
.pin_banks = rk3576_pin_banks,
4149+
.nr_banks = ARRAY_SIZE(rk3576_pin_banks),
4150+
.label = "RK3576-GPIO",
4151+
.type = RK3576,
4152+
.pull_calc_reg = rk3576_calc_pull_reg_and_bit,
4153+
.drv_calc_reg = rk3576_calc_drv_reg_and_bit,
4154+
.schmitt_calc_reg = rk3576_calc_schmitt_reg_and_bit,
4155+
};
4156+
39524157
static struct rockchip_pin_bank rk3588_pin_banks[] = {
39534158
RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
39544159
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
@@ -4005,6 +4210,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
40054210
.data = &rk3399_pin_ctrl },
40064211
{ .compatible = "rockchip,rk3568-pinctrl",
40074212
.data = &rk3568_pin_ctrl },
4213+
{ .compatible = "rockchip,rk3576-pinctrl",
4214+
.data = &rk3576_pin_ctrl },
40084215
{ .compatible = "rockchip,rk3588-pinctrl",
40094216
.data = &rk3588_pin_ctrl },
40104217
{},

‎drivers/pinctrl/pinctrl-rockchip.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,7 @@ enum rockchip_pinctrl_type {
197197
RK3368,
198198
RK3399,
199199
RK3568,
200+
RK3576,
200201
RK3588,
201202
};
202203

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