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Merge tag 'amd-drm-next-5.7-2020-03-10' of git://people.freedesktop.org/~agd5f/linux into drm-next
amd-drm-next-5.7-2020-03-10: amdgpu: - SR-IOV fixes - Fix up fallout from drm load/unload callback removal - Navi, renoir power management watermark fixes - Refactor smu parameter handling - Display FEC fixes - Display DCC fixes - HDCP fixes - Add support for USB-C PD firmware updates - Pollock detection fix - Rework compute ring priority handling - RAS fixes - Misc cleanups amdkfd: - Consolidate more gfx config details in amdgpu - Consolidate bo alloc flags - Improve code comments - SDMA MQD fixes - Misc cleanups gpu scheduler: - Add suport for modifying the sched list uapi: - Clarify comments about GEM_CREATE flags that are not used by userspace. The kernel driver has always prevented userspace from using these. They are only used internally in the kernel driver. Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 9e12da0 + 5d11e37 commit 69ddce0

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‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -579,6 +579,7 @@ struct amdgpu_asic_funcs {
579579
/* invalidate hdp read cache */
580580
void (*invalidate_hdp)(struct amdgpu_device *adev,
581581
struct amdgpu_ring *ring);
582+
void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev);
582583
/* check if the asic needs a full reset of if soft reset will work */
583584
bool (*need_full_reset)(struct amdgpu_device *adev);
584585
/* initialize doorbell layout for specific asic*/

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929
#include <linux/module.h>
3030
#include <linux/dma-buf.h>
3131
#include "amdgpu_xgmi.h"
32+
#include <uapi/linux/kfd_ioctl.h>
3233

3334
static const unsigned int compute_vmid_bitmap = 0xFF00;
3435

@@ -224,7 +225,7 @@ void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
224225

225226
int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
226227
void **mem_obj, uint64_t *gpu_addr,
227-
void **cpu_ptr, bool mqd_gfx9)
228+
void **cpu_ptr, bool cp_mqd_gfx9)
228229
{
229230
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
230231
struct amdgpu_bo *bo = NULL;
@@ -240,8 +241,8 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
240241
bp.type = ttm_bo_type_kernel;
241242
bp.resv = NULL;
242243

243-
if (mqd_gfx9)
244-
bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9;
244+
if (cp_mqd_gfx9)
245+
bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
245246

246247
r = amdgpu_bo_create(adev, &bp, &bo);
247248
if (r) {
@@ -501,10 +502,11 @@ int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
501502
metadata_size, &metadata_flags);
502503
if (flags) {
503504
*flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
504-
ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT;
505+
KFD_IOC_ALLOC_MEM_FLAGS_VRAM
506+
: KFD_IOC_ALLOC_MEM_FLAGS_GTT;
505507

506508
if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
507-
*flags |= ALLOC_MEM_FLAGS_PUBLIC;
509+
*flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
508510
}
509511

510512
out_put:

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -242,6 +242,9 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
242242
void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
243243
void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo);
244244

245+
int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
246+
struct tile_config *config);
247+
245248
/* KGD2KFD callbacks */
246249
int kgd2kfd_init(void);
247250
void kgd2kfd_exit(void);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -319,7 +319,6 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = {
319319
.address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
320320
.get_atc_vmid_pasid_mapping_info =
321321
kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
322-
.get_tile_config = kgd_gfx_v9_get_tile_config,
323322
.set_vm_context_page_table_base = kgd_set_vm_context_page_table_base,
324323
.get_hive_id = amdgpu_amdkfd_get_hive_id,
325324
};

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

Lines changed: 0 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -42,38 +42,6 @@ enum hqd_dequeue_request_type {
4242
SAVE_WAVES
4343
};
4444

45-
/* Because of REG_GET_FIELD() being used, we put this function in the
46-
* asic specific file.
47-
*/
48-
static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
49-
struct tile_config *config)
50-
{
51-
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
52-
53-
config->gb_addr_config = adev->gfx.config.gb_addr_config;
54-
#if 0
55-
/* TODO - confirm REG_GET_FIELD x2, should be OK as is... but
56-
* MC_ARB_RAMCFG register doesn't exist on Vega10 - initial amdgpu
57-
* changes commented out related code, doing the same here for now but
58-
* need to sync with Ken et al
59-
*/
60-
config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
61-
MC_ARB_RAMCFG, NOOFBANK);
62-
config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
63-
MC_ARB_RAMCFG, NOOFRANKS);
64-
#endif
65-
66-
config->tile_config_ptr = adev->gfx.config.tile_mode_array;
67-
config->num_tile_configs =
68-
ARRAY_SIZE(adev->gfx.config.tile_mode_array);
69-
config->macro_tile_config_ptr =
70-
adev->gfx.config.macrotile_mode_array;
71-
config->num_macro_tile_configs =
72-
ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
73-
74-
return 0;
75-
}
76-
7745
static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
7846
{
7947
return (struct amdgpu_device *)kgd;
@@ -805,7 +773,6 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
805773
.address_watch_get_offset = kgd_address_watch_get_offset,
806774
.get_atc_vmid_pasid_mapping_info =
807775
get_atc_vmid_pasid_mapping_info,
808-
.get_tile_config = amdgpu_amdkfd_get_tile_config,
809776
.set_vm_context_page_table_base = set_vm_context_page_table_base,
810777
.get_hive_id = amdgpu_amdkfd_get_hive_id,
811778
.get_unique_id = amdgpu_amdkfd_get_unique_id,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

Lines changed: 0 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -84,31 +84,6 @@ union TCP_WATCH_CNTL_BITS {
8484
float f32All;
8585
};
8686

87-
/* Because of REG_GET_FIELD() being used, we put this function in the
88-
* asic specific file.
89-
*/
90-
static int get_tile_config(struct kgd_dev *kgd,
91-
struct tile_config *config)
92-
{
93-
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
94-
95-
config->gb_addr_config = adev->gfx.config.gb_addr_config;
96-
config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
97-
MC_ARB_RAMCFG, NOOFBANK);
98-
config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
99-
MC_ARB_RAMCFG, NOOFRANKS);
100-
101-
config->tile_config_ptr = adev->gfx.config.tile_mode_array;
102-
config->num_tile_configs =
103-
ARRAY_SIZE(adev->gfx.config.tile_mode_array);
104-
config->macro_tile_config_ptr =
105-
adev->gfx.config.macrotile_mode_array;
106-
config->num_macro_tile_configs =
107-
ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
108-
109-
return 0;
110-
}
111-
11287
static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
11388
{
11489
return (struct amdgpu_device *)kgd;
@@ -730,7 +705,6 @@ const struct kfd2kgd_calls gfx_v7_kfd2kgd = {
730705
.address_watch_get_offset = kgd_address_watch_get_offset,
731706
.get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
732707
.set_scratch_backing_va = set_scratch_backing_va,
733-
.get_tile_config = get_tile_config,
734708
.set_vm_context_page_table_base = set_vm_context_page_table_base,
735709
.read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
736710
};

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

Lines changed: 0 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -41,31 +41,6 @@ enum hqd_dequeue_request_type {
4141
RESET_WAVES
4242
};
4343

44-
/* Because of REG_GET_FIELD() being used, we put this function in the
45-
* asic specific file.
46-
*/
47-
static int get_tile_config(struct kgd_dev *kgd,
48-
struct tile_config *config)
49-
{
50-
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
51-
52-
config->gb_addr_config = adev->gfx.config.gb_addr_config;
53-
config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
54-
MC_ARB_RAMCFG, NOOFBANK);
55-
config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
56-
MC_ARB_RAMCFG, NOOFRANKS);
57-
58-
config->tile_config_ptr = adev->gfx.config.tile_mode_array;
59-
config->num_tile_configs =
60-
ARRAY_SIZE(adev->gfx.config.tile_mode_array);
61-
config->macro_tile_config_ptr =
62-
adev->gfx.config.macrotile_mode_array;
63-
config->num_macro_tile_configs =
64-
ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
65-
66-
return 0;
67-
}
68-
6944
static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
7045
{
7146
return (struct amdgpu_device *)kgd;
@@ -676,6 +651,5 @@ const struct kfd2kgd_calls gfx_v8_kfd2kgd = {
676651
.get_atc_vmid_pasid_mapping_info =
677652
get_atc_vmid_pasid_mapping_info,
678653
.set_scratch_backing_va = set_scratch_backing_va,
679-
.get_tile_config = get_tile_config,
680654
.set_vm_context_page_table_base = set_vm_context_page_table_base,
681655
};

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

Lines changed: 0 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -48,28 +48,6 @@ enum hqd_dequeue_request_type {
4848
RESET_WAVES
4949
};
5050

51-
52-
/* Because of REG_GET_FIELD() being used, we put this function in the
53-
* asic specific file.
54-
*/
55-
int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
56-
struct tile_config *config)
57-
{
58-
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
59-
60-
config->gb_addr_config = adev->gfx.config.gb_addr_config;
61-
62-
config->tile_config_ptr = adev->gfx.config.tile_mode_array;
63-
config->num_tile_configs =
64-
ARRAY_SIZE(adev->gfx.config.tile_mode_array);
65-
config->macro_tile_config_ptr =
66-
adev->gfx.config.macrotile_mode_array;
67-
config->num_macro_tile_configs =
68-
ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
69-
70-
return 0;
71-
}
72-
7351
static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
7452
{
7553
return (struct amdgpu_device *)kgd;
@@ -736,7 +714,6 @@ const struct kfd2kgd_calls gfx_v9_kfd2kgd = {
736714
.address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
737715
.get_atc_vmid_pasid_mapping_info =
738716
kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
739-
.get_tile_config = kgd_gfx_v9_get_tile_config,
740717
.set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
741718
.get_hive_id = amdgpu_amdkfd_get_hive_id,
742719
.get_unique_id = amdgpu_amdkfd_get_unique_id,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -60,5 +60,3 @@ uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd,
6060

6161
bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
6262
uint8_t vmid, uint16_t *p_pasid);
63-
int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
64-
struct tile_config *config);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

Lines changed: 38 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929
#include "amdgpu_vm.h"
3030
#include "amdgpu_amdkfd.h"
3131
#include "amdgpu_dma_buf.h"
32+
#include <uapi/linux/kfd_ioctl.h>
3233

3334
/* BO flag to indicate a KFD userptr BO */
3435
#define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63)
@@ -400,18 +401,18 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
400401
static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
401402
{
402403
struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
403-
bool coherent = mem->alloc_flags & ALLOC_MEM_FLAGS_COHERENT;
404+
bool coherent = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT;
404405
uint32_t mapping_flags;
405406

406407
mapping_flags = AMDGPU_VM_PAGE_READABLE;
407-
if (mem->alloc_flags & ALLOC_MEM_FLAGS_WRITABLE)
408+
if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
408409
mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
409-
if (mem->alloc_flags & ALLOC_MEM_FLAGS_EXECUTABLE)
410+
if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
410411
mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
411412

412413
switch (adev->asic_type) {
413414
case CHIP_ARCTURUS:
414-
if (mem->alloc_flags & ALLOC_MEM_FLAGS_VRAM) {
415+
if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
415416
if (bo_adev == adev)
416417
mapping_flags |= coherent ?
417418
AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
@@ -1160,24 +1161,24 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
11601161
/*
11611162
* Check on which domain to allocate BO
11621163
*/
1163-
if (flags & ALLOC_MEM_FLAGS_VRAM) {
1164+
if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
11641165
domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
11651166
alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1166-
alloc_flags |= (flags & ALLOC_MEM_FLAGS_PUBLIC) ?
1167+
alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
11671168
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED :
11681169
AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
1169-
} else if (flags & ALLOC_MEM_FLAGS_GTT) {
1170+
} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
11701171
domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
11711172
alloc_flags = 0;
1172-
} else if (flags & ALLOC_MEM_FLAGS_USERPTR) {
1173+
} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
11731174
domain = AMDGPU_GEM_DOMAIN_GTT;
11741175
alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
11751176
alloc_flags = 0;
11761177
if (!offset || !*offset)
11771178
return -EINVAL;
11781179
user_addr = untagged_addr(*offset);
1179-
} else if (flags & (ALLOC_MEM_FLAGS_DOORBELL |
1180-
ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1180+
} else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1181+
KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
11811182
domain = AMDGPU_GEM_DOMAIN_GTT;
11821183
alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
11831184
bo_type = ttm_bo_type_sg;
@@ -1198,7 +1199,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
11981199
}
11991200
INIT_LIST_HEAD(&(*mem)->bo_va_list);
12001201
mutex_init(&(*mem)->lock);
1201-
(*mem)->aql_queue = !!(flags & ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1202+
(*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
12021203

12031204
/* Workaround for AQL queue wraparound bug. Map the same
12041205
* memory twice. That means we only actually allocate half
@@ -1680,10 +1681,12 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
16801681

16811682
INIT_LIST_HEAD(&(*mem)->bo_va_list);
16821683
mutex_init(&(*mem)->lock);
1684+
16831685
(*mem)->alloc_flags =
16841686
((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
1685-
ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT) |
1686-
ALLOC_MEM_FLAGS_WRITABLE | ALLOC_MEM_FLAGS_EXECUTABLE;
1687+
KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
1688+
| KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
1689+
| KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
16871690

16881691
(*mem)->bo = amdgpu_bo_ref(bo);
16891692
(*mem)->va = va;
@@ -2242,3 +2245,25 @@ int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
22422245
kfree(mem);
22432246
return 0;
22442247
}
2248+
2249+
/* Returns GPU-specific tiling mode information */
2250+
int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
2251+
struct tile_config *config)
2252+
{
2253+
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
2254+
2255+
config->gb_addr_config = adev->gfx.config.gb_addr_config;
2256+
config->tile_config_ptr = adev->gfx.config.tile_mode_array;
2257+
config->num_tile_configs =
2258+
ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2259+
config->macro_tile_config_ptr =
2260+
adev->gfx.config.macrotile_mode_array;
2261+
config->num_macro_tile_configs =
2262+
ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2263+
2264+
/* Those values are not set from GFX9 onwards */
2265+
config->num_banks = adev->gfx.config.num_banks;
2266+
config->num_ranks = adev->gfx.config.num_ranks;
2267+
2268+
return 0;
2269+
}

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