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KVM: selftests: Add array order helpers to riscv get-reg-list
Add a couple macros to use when filling arrays in order to ensure the elements are placed in the right order, regardless of the order we prefer to read them. And immediately apply the new macro to resorting the ISA extension lists alphabetically. Signed-off-by: Andrew Jones <[email protected]> Reviewed-by: Haibo Xu <[email protected]> Signed-off-by: Anup Patel <[email protected]>
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tools/testing/selftests/kvm/riscv/get-reg-list.c

Lines changed: 47 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,8 @@ bool filter_reg(__u64 reg)
2525
* the visibility of the ISA_EXT register itself.
2626
*
2727
* Based on above, we should filter-out all ISA_EXT registers.
28+
*
29+
* Note: The below list is alphabetically sorted.
2830
*/
2931
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_A:
3032
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_C:
@@ -33,21 +35,21 @@ bool filter_reg(__u64 reg)
3335
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_H:
3436
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I:
3537
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M:
36-
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT:
38+
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V:
39+
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA:
3740
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC:
3841
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL:
39-
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
40-
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM:
41-
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ:
42-
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB:
43-
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA:
44-
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V:
4542
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVNAPOT:
43+
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT:
4644
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBA:
45+
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB:
4746
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBS:
47+
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM:
48+
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ:
4849
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR:
4950
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR:
5051
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
52+
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
5153
case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
5254
return true;
5355
/* AIA registers are always available when Ssaia can't be disabled */
@@ -311,35 +313,38 @@ static const char *fp_d_id_to_str(const char *prefix, __u64 id)
311313
return NULL;
312314
}
313315

316+
#define KVM_ISA_EXT_ARR(ext) \
317+
[KVM_RISCV_ISA_EXT_##ext] = "KVM_RISCV_ISA_EXT_" #ext
318+
314319
static const char *isa_ext_id_to_str(__u64 id)
315320
{
316321
/* reg_off is the offset into unsigned long kvm_isa_ext_arr[] */
317322
__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT);
318323

319324
static const char * const kvm_isa_ext_reg_name[] = {
320-
"KVM_RISCV_ISA_EXT_A",
321-
"KVM_RISCV_ISA_EXT_C",
322-
"KVM_RISCV_ISA_EXT_D",
323-
"KVM_RISCV_ISA_EXT_F",
324-
"KVM_RISCV_ISA_EXT_H",
325-
"KVM_RISCV_ISA_EXT_I",
326-
"KVM_RISCV_ISA_EXT_M",
327-
"KVM_RISCV_ISA_EXT_SVPBMT",
328-
"KVM_RISCV_ISA_EXT_SSTC",
329-
"KVM_RISCV_ISA_EXT_SVINVAL",
330-
"KVM_RISCV_ISA_EXT_ZIHINTPAUSE",
331-
"KVM_RISCV_ISA_EXT_ZICBOM",
332-
"KVM_RISCV_ISA_EXT_ZICBOZ",
333-
"KVM_RISCV_ISA_EXT_ZBB",
334-
"KVM_RISCV_ISA_EXT_SSAIA",
335-
"KVM_RISCV_ISA_EXT_V",
336-
"KVM_RISCV_ISA_EXT_SVNAPOT",
337-
"KVM_RISCV_ISA_EXT_ZBA",
338-
"KVM_RISCV_ISA_EXT_ZBS",
339-
"KVM_RISCV_ISA_EXT_ZICNTR",
340-
"KVM_RISCV_ISA_EXT_ZICSR",
341-
"KVM_RISCV_ISA_EXT_ZIFENCEI",
342-
"KVM_RISCV_ISA_EXT_ZIHPM",
325+
KVM_ISA_EXT_ARR(A),
326+
KVM_ISA_EXT_ARR(C),
327+
KVM_ISA_EXT_ARR(D),
328+
KVM_ISA_EXT_ARR(F),
329+
KVM_ISA_EXT_ARR(H),
330+
KVM_ISA_EXT_ARR(I),
331+
KVM_ISA_EXT_ARR(M),
332+
KVM_ISA_EXT_ARR(V),
333+
KVM_ISA_EXT_ARR(SSAIA),
334+
KVM_ISA_EXT_ARR(SSTC),
335+
KVM_ISA_EXT_ARR(SVINVAL),
336+
KVM_ISA_EXT_ARR(SVNAPOT),
337+
KVM_ISA_EXT_ARR(SVPBMT),
338+
KVM_ISA_EXT_ARR(ZBA),
339+
KVM_ISA_EXT_ARR(ZBB),
340+
KVM_ISA_EXT_ARR(ZBS),
341+
KVM_ISA_EXT_ARR(ZICBOM),
342+
KVM_ISA_EXT_ARR(ZICBOZ),
343+
KVM_ISA_EXT_ARR(ZICNTR),
344+
KVM_ISA_EXT_ARR(ZICSR),
345+
KVM_ISA_EXT_ARR(ZIFENCEI),
346+
KVM_ISA_EXT_ARR(ZIHINTPAUSE),
347+
KVM_ISA_EXT_ARR(ZIHPM),
343348
};
344349

345350
if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {
@@ -353,19 +358,22 @@ static const char *isa_ext_id_to_str(__u64 id)
353358
return kvm_isa_ext_reg_name[reg_off];
354359
}
355360

361+
#define KVM_SBI_EXT_ARR(ext) \
362+
[ext] = "KVM_REG_RISCV_SBI_SINGLE | " #ext
363+
356364
static const char *sbi_ext_single_id_to_str(__u64 reg_off)
357365
{
358366
/* reg_off is KVM_RISCV_SBI_EXT_ID */
359367
static const char * const kvm_sbi_ext_reg_name[] = {
360-
"KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01",
361-
"KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME",
362-
"KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI",
363-
"KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE",
364-
"KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST",
365-
"KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM",
366-
"KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU",
367-
"KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL",
368-
"KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR",
368+
KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_V01),
369+
KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_TIME),
370+
KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_IPI),
371+
KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_RFENCE),
372+
KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SRST),
373+
KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_HSM),
374+
KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_PMU),
375+
KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL),
376+
KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR),
369377
};
370378

371379
if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name)) {

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