@@ -25,6 +25,8 @@ bool filter_reg(__u64 reg)
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* the visibility of the ISA_EXT register itself.
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*
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* Based on above, we should filter-out all ISA_EXT registers.
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+ *
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+ * Note: The below list is alphabetically sorted.
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*/
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_A :
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_C :
@@ -33,21 +35,21 @@ bool filter_reg(__u64 reg)
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_H :
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I :
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M :
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- case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT :
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+ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V :
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+ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA :
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC :
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL :
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- case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE :
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- case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM :
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- case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ :
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- case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB :
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- case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA :
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- case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V :
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVNAPOT :
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+ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT :
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBA :
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+ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB :
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBS :
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+ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM :
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+ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ :
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR :
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR :
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI :
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+ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE :
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case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM :
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return true;
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/* AIA registers are always available when Ssaia can't be disabled */
@@ -311,35 +313,38 @@ static const char *fp_d_id_to_str(const char *prefix, __u64 id)
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return NULL ;
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}
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+ #define KVM_ISA_EXT_ARR (ext ) \
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+ [KVM_RISCV_ISA_EXT_##ext] = "KVM_RISCV_ISA_EXT_" #ext
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+
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static const char * isa_ext_id_to_str (__u64 id )
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{
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/* reg_off is the offset into unsigned long kvm_isa_ext_arr[] */
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__u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT );
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static const char * const kvm_isa_ext_reg_name [] = {
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- "KVM_RISCV_ISA_EXT_A" ,
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- "KVM_RISCV_ISA_EXT_C" ,
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- "KVM_RISCV_ISA_EXT_D" ,
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- "KVM_RISCV_ISA_EXT_F" ,
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- "KVM_RISCV_ISA_EXT_H" ,
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- "KVM_RISCV_ISA_EXT_I" ,
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- "KVM_RISCV_ISA_EXT_M" ,
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- "KVM_RISCV_ISA_EXT_SVPBMT" ,
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- "KVM_RISCV_ISA_EXT_SSTC" ,
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- "KVM_RISCV_ISA_EXT_SVINVAL" ,
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- "KVM_RISCV_ISA_EXT_ZIHINTPAUSE" ,
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- "KVM_RISCV_ISA_EXT_ZICBOM" ,
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- "KVM_RISCV_ISA_EXT_ZICBOZ" ,
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- "KVM_RISCV_ISA_EXT_ZBB" ,
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- "KVM_RISCV_ISA_EXT_SSAIA" ,
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- "KVM_RISCV_ISA_EXT_V" ,
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- "KVM_RISCV_ISA_EXT_SVNAPOT" ,
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- "KVM_RISCV_ISA_EXT_ZBA" ,
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- "KVM_RISCV_ISA_EXT_ZBS" ,
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- "KVM_RISCV_ISA_EXT_ZICNTR" ,
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- "KVM_RISCV_ISA_EXT_ZICSR" ,
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- "KVM_RISCV_ISA_EXT_ZIFENCEI" ,
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- "KVM_RISCV_ISA_EXT_ZIHPM" ,
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+ KVM_ISA_EXT_ARR ( A ) ,
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+ KVM_ISA_EXT_ARR ( C ) ,
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+ KVM_ISA_EXT_ARR ( D ) ,
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+ KVM_ISA_EXT_ARR ( F ) ,
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+ KVM_ISA_EXT_ARR ( H ) ,
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+ KVM_ISA_EXT_ARR ( I ) ,
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+ KVM_ISA_EXT_ARR ( M ) ,
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+ KVM_ISA_EXT_ARR ( V ) ,
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+ KVM_ISA_EXT_ARR ( SSAIA ) ,
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+ KVM_ISA_EXT_ARR ( SSTC ) ,
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+ KVM_ISA_EXT_ARR ( SVINVAL ) ,
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+ KVM_ISA_EXT_ARR ( SVNAPOT ) ,
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+ KVM_ISA_EXT_ARR ( SVPBMT ) ,
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+ KVM_ISA_EXT_ARR ( ZBA ) ,
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+ KVM_ISA_EXT_ARR ( ZBB ) ,
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+ KVM_ISA_EXT_ARR ( ZBS ) ,
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+ KVM_ISA_EXT_ARR ( ZICBOM ) ,
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+ KVM_ISA_EXT_ARR ( ZICBOZ ) ,
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+ KVM_ISA_EXT_ARR ( ZICNTR ) ,
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+ KVM_ISA_EXT_ARR ( ZICSR ) ,
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+ KVM_ISA_EXT_ARR ( ZIFENCEI ) ,
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+ KVM_ISA_EXT_ARR ( ZIHINTPAUSE ) ,
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+ KVM_ISA_EXT_ARR ( ZIHPM ) ,
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};
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if (reg_off >= ARRAY_SIZE (kvm_isa_ext_reg_name )) {
@@ -353,19 +358,22 @@ static const char *isa_ext_id_to_str(__u64 id)
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return kvm_isa_ext_reg_name [reg_off ];
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}
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+ #define KVM_SBI_EXT_ARR (ext ) \
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+ [ext] = "KVM_REG_RISCV_SBI_SINGLE | " #ext
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+
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static const char * sbi_ext_single_id_to_str (__u64 reg_off )
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{
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/* reg_off is KVM_RISCV_SBI_EXT_ID */
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static const char * const kvm_sbi_ext_reg_name [] = {
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- "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01" ,
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- "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME" ,
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- "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI" ,
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- "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE" ,
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- "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST" ,
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- "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM" ,
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- "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU" ,
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- "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL" ,
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- "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR" ,
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+ KVM_SBI_EXT_ARR ( KVM_RISCV_SBI_EXT_V01 ) ,
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+ KVM_SBI_EXT_ARR ( KVM_RISCV_SBI_EXT_TIME ) ,
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+ KVM_SBI_EXT_ARR ( KVM_RISCV_SBI_EXT_IPI ) ,
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+ KVM_SBI_EXT_ARR ( KVM_RISCV_SBI_EXT_RFENCE ) ,
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+ KVM_SBI_EXT_ARR ( KVM_RISCV_SBI_EXT_SRST ) ,
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+ KVM_SBI_EXT_ARR ( KVM_RISCV_SBI_EXT_HSM ) ,
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+ KVM_SBI_EXT_ARR ( KVM_RISCV_SBI_EXT_PMU ) ,
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+ KVM_SBI_EXT_ARR ( KVM_RISCV_SBI_EXT_EXPERIMENTAL ) ,
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+ KVM_SBI_EXT_ARR ( KVM_RISCV_SBI_EXT_VENDOR ) ,
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};
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if (reg_off >= ARRAY_SIZE (kvm_sbi_ext_reg_name )) {
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