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/* 0x14b - 0x152 Holdover */
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/* 0x153 - 0x15f PLL1 Configuration */
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+ #define LMK04832_REG_PLL1_LD 0x15f
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+ #define LMK04832_BIT_PLL1_LD_MUX GENMASK(7, 3)
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+ #define LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK 0x07
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+ #define LMK04832_BIT_PLL1_LD_TYPE GENMASK(2, 0)
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+ #define LMK04832_VAL_PLL1_LD_TYPE_OUT_PP 0x03
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/* 0x160 - 0x16e PLL2 Configuration */
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#define LMK04832_REG_PLL2_R_MSB 0x160
@@ -206,6 +211,7 @@ enum lmk04832_rdbk_type {
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RDBK_CLKIN_SEL0 ,
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RDBK_CLKIN_SEL1 ,
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RDBK_RESET ,
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+ RDBK_PLL1_LD ,
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};
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struct lmk_dclk {
@@ -1346,6 +1352,10 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
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{
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int reg ;
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int ret ;
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+ int val = FIELD_PREP (LMK04832_BIT_CLKIN_SEL_MUX ,
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+ LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK ) |
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+ FIELD_PREP (LMK04832_BIT_CLKIN_SEL_TYPE ,
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+ LMK04832_VAL_CLKIN_SEL_TYPE_OUT );
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dev_info (lmk -> dev , "setting up 4-wire mode\n" );
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ret = regmap_write (lmk -> regmap , LMK04832_REG_RST3W ,
@@ -1363,15 +1373,18 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
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case RDBK_RESET :
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reg = LMK04832_REG_CLKIN_RST ;
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break ;
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+ case RDBK_PLL1_LD :
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+ reg = LMK04832_REG_PLL1_LD ;
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+ val = FIELD_PREP (LMK04832_BIT_PLL1_LD_MUX ,
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+ LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK ) |
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+ FIELD_PREP (LMK04832_BIT_PLL1_LD_TYPE ,
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+ LMK04832_VAL_PLL1_LD_TYPE_OUT_PP );
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+ break ;
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default :
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return - EINVAL ;
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}
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- return regmap_write (lmk -> regmap , reg ,
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- FIELD_PREP (LMK04832_BIT_CLKIN_SEL_MUX ,
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- LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK ) |
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- FIELD_PREP (LMK04832_BIT_CLKIN_SEL_TYPE ,
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- LMK04832_VAL_CLKIN_SEL_TYPE_OUT ));
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+ return regmap_write (lmk -> regmap , reg , val );
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}
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static int lmk04832_probe (struct spi_device * spi )
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