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aharonl-nvidiajgunthorpe
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RDMA/mlx5: Store in the cache mkeys instead of mrs
Currently, the driver stores mlx5_ib_mr struct in the cache entries, although the only use of the cached MR is the mkey. Store only the mkey in the cache. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Aharon Landau <[email protected]> Signed-off-by: Leon Romanovsky <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]>
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drivers/infiniband/hw/mlx5/mlx5_ib.h

Lines changed: 11 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -619,6 +619,7 @@ struct mlx5_ib_mkey {
619619
unsigned int ndescs;
620620
struct wait_queue_head wait;
621621
refcount_t usecount;
622+
struct mlx5_cache_ent *cache_ent;
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};
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#define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
@@ -641,18 +642,9 @@ struct mlx5_ib_mr {
641642
struct ib_mr ibmr;
642643
struct mlx5_ib_mkey mmkey;
643644

644-
/* User MR data */
645-
struct mlx5_cache_ent *cache_ent;
646-
/* Everything after cache_ent is zero'd when MR allocated */
647645
struct ib_umem *umem;
648646

649647
union {
650-
/* Used only while the MR is in the cache */
651-
struct {
652-
u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
653-
struct mlx5_async_work cb_work;
654-
};
655-
656648
/* Used only by kernel MRs (umem == NULL) */
657649
struct {
658650
void *descs;
@@ -692,12 +684,6 @@ struct mlx5_ib_mr {
692684
};
693685
};
694686

695-
/* Zero the fields in the mr that are variant depending on usage */
696-
static inline void mlx5_clear_mr(struct mlx5_ib_mr *mr)
697-
{
698-
memset_after(mr, 0, cache_ent);
699-
}
700-
701687
static inline bool is_odp_mr(struct mlx5_ib_mr *mr)
702688
{
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return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
@@ -768,6 +754,16 @@ struct mlx5_cache_ent {
768754
struct delayed_work dwork;
769755
};
770756

757+
struct mlx5r_async_create_mkey {
758+
union {
759+
u32 in[MLX5_ST_SZ_BYTES(create_mkey_in)];
760+
u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
761+
};
762+
struct mlx5_async_work cb_work;
763+
struct mlx5_cache_ent *ent;
764+
u32 mkey;
765+
};
766+
771767
struct mlx5_mr_cache {
772768
struct workqueue_struct *wq;
773769
struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];

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