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nxpfranklibp3tk0v
nxpfrankli
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bp3tk0v
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EDAC/fsl_ddr: Pass down fsl_mc_pdata in ddr_in32() and ddr_out32()
Pass down fsl_mc_pdata in helper functions ddr_in32() and ddr_out32() to prepare for adding iMX9 support. The iMX9 has a slightly different register layout. No functional change. Signed-off-by: Frank Li <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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‎drivers/edac/fsl_ddr_edac.c

Lines changed: 34 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -35,13 +35,17 @@ static u32 orig_ddr_err_disable;
3535
static u32 orig_ddr_err_sbe;
3636
static bool little_endian;
3737

38-
static inline u32 ddr_in32(void __iomem *addr)
38+
static inline u32 ddr_in32(struct fsl_mc_pdata *pdata, unsigned int off)
3939
{
40+
void __iomem *addr = pdata->mc_vbase + off;
41+
4042
return little_endian ? ioread32(addr) : ioread32be(addr);
4143
}
4244

43-
static inline void ddr_out32(void __iomem *addr, u32 value)
45+
static inline void ddr_out32(struct fsl_mc_pdata *pdata, unsigned int off, u32 value)
4446
{
47+
void __iomem *addr = pdata->mc_vbase + off;
48+
4549
if (little_endian)
4650
iowrite32(value, addr);
4751
else
@@ -60,7 +64,7 @@ static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
6064
struct mem_ctl_info *mci = to_mci(dev);
6165
struct fsl_mc_pdata *pdata = mci->pvt_info;
6266
return sprintf(data, "0x%08x",
63-
ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI));
67+
ddr_in32(pdata, FSL_MC_DATA_ERR_INJECT_HI));
6468
}
6569

6670
static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
@@ -70,7 +74,7 @@ static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
7074
struct mem_ctl_info *mci = to_mci(dev);
7175
struct fsl_mc_pdata *pdata = mci->pvt_info;
7276
return sprintf(data, "0x%08x",
73-
ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO));
77+
ddr_in32(pdata, FSL_MC_DATA_ERR_INJECT_LO));
7478
}
7579

7680
static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
@@ -80,7 +84,7 @@ static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
8084
struct mem_ctl_info *mci = to_mci(dev);
8185
struct fsl_mc_pdata *pdata = mci->pvt_info;
8286
return sprintf(data, "0x%08x",
83-
ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
87+
ddr_in32(pdata, FSL_MC_ECC_ERR_INJECT));
8488
}
8589

8690
static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
@@ -97,7 +101,7 @@ static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
97101
if (rc)
98102
return rc;
99103

100-
ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI, val);
104+
ddr_out32(pdata, FSL_MC_DATA_ERR_INJECT_HI, val);
101105
return count;
102106
}
103107
return 0;
@@ -117,7 +121,7 @@ static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
117121
if (rc)
118122
return rc;
119123

120-
ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO, val);
124+
ddr_out32(pdata, FSL_MC_DATA_ERR_INJECT_LO, val);
121125
return count;
122126
}
123127
return 0;
@@ -137,7 +141,7 @@ static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
137141
if (rc)
138142
return rc;
139143

140-
ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT, val);
144+
ddr_out32(pdata, FSL_MC_ECC_ERR_INJECT, val);
141145
return count;
142146
}
143147
return 0;
@@ -286,7 +290,7 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
286290
int bad_data_bit;
287291
int bad_ecc_bit;
288292

289-
err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
293+
err_detect = ddr_in32(pdata, FSL_MC_ERR_DETECT);
290294
if (!err_detect)
291295
return;
292296

@@ -295,23 +299,23 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
295299

296300
/* no more processing if not ECC bit errors */
297301
if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
298-
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
302+
ddr_out32(pdata, FSL_MC_ERR_DETECT, err_detect);
299303
return;
300304
}
301305

302-
syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
306+
syndrome = ddr_in32(pdata, FSL_MC_CAPTURE_ECC);
303307

304308
/* Mask off appropriate bits of syndrome based on bus width */
305-
bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
309+
bus_width = (ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG) &
306310
DSC_DBW_MASK) ? 32 : 64;
307311
if (bus_width == 64)
308312
syndrome &= 0xff;
309313
else
310314
syndrome &= 0xffff;
311315

312316
err_addr = make64(
313-
ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
314-
ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
317+
ddr_in32(pdata, FSL_MC_CAPTURE_EXT_ADDRESS),
318+
ddr_in32(pdata, FSL_MC_CAPTURE_ADDRESS));
315319
pfn = err_addr >> PAGE_SHIFT;
316320

317321
for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
@@ -320,8 +324,8 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
320324
break;
321325
}
322326

323-
cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
324-
cap_low = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
327+
cap_high = ddr_in32(pdata, FSL_MC_CAPTURE_DATA_HI);
328+
cap_low = ddr_in32(pdata, FSL_MC_CAPTURE_DATA_LO);
325329

326330
/*
327331
* Analyze single-bit errors on 64-bit wide buses
@@ -367,7 +371,7 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
367371
row_index, 0, -1,
368372
mci->ctl_name, "");
369373

370-
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
374+
ddr_out32(pdata, FSL_MC_ERR_DETECT, err_detect);
371375
}
372376

373377
static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
@@ -376,7 +380,7 @@ static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
376380
struct fsl_mc_pdata *pdata = mci->pvt_info;
377381
u32 err_detect;
378382

379-
err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
383+
err_detect = ddr_in32(pdata, FSL_MC_ERR_DETECT);
380384
if (!err_detect)
381385
return IRQ_NONE;
382386

@@ -396,7 +400,7 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
396400
u32 cs_bnds;
397401
int index;
398402

399-
sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
403+
sdram_ctl = ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG);
400404

401405
sdtype = sdram_ctl & DSC_SDTYPE_MASK;
402406
if (sdram_ctl & DSC_RD_EN) {
@@ -444,7 +448,7 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
444448
csrow = mci->csrows[index];
445449
dimm = csrow->channels[0]->dimm;
446450

447-
cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
451+
cs_bnds = ddr_in32(pdata, FSL_MC_CS_BNDS_0 +
448452
(index * FSL_MC_CS_BNDS_OFS));
449453

450454
start = (cs_bnds & 0xffff0000) >> 16;
@@ -531,7 +535,7 @@ int fsl_mc_err_probe(struct platform_device *op)
531535
goto err;
532536
}
533537

534-
sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
538+
sdram_ctl = ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG);
535539
if (!(sdram_ctl & DSC_ECC_EN)) {
536540
/* no ECC */
537541
pr_warn("%s: No ECC DIMMs discovered\n", __func__);
@@ -558,11 +562,11 @@ int fsl_mc_err_probe(struct platform_device *op)
558562
fsl_ddr_init_csrows(mci);
559563

560564
/* store the original error disable bits */
561-
orig_ddr_err_disable = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
562-
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
565+
orig_ddr_err_disable = ddr_in32(pdata, FSL_MC_ERR_DISABLE);
566+
ddr_out32(pdata, FSL_MC_ERR_DISABLE, 0);
563567

564568
/* clear all error bits */
565-
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
569+
ddr_out32(pdata, FSL_MC_ERR_DETECT, ~0);
566570

567571
res = edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups);
568572
if (res) {
@@ -571,15 +575,15 @@ int fsl_mc_err_probe(struct platform_device *op)
571575
}
572576

573577
if (edac_op_state == EDAC_OPSTATE_INT) {
574-
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
578+
ddr_out32(pdata, FSL_MC_ERR_INT_EN,
575579
DDR_EIE_MBEE | DDR_EIE_SBEE);
576580

577581
/* store the original error management threshold */
578-
orig_ddr_err_sbe = ddr_in32(pdata->mc_vbase +
582+
orig_ddr_err_sbe = ddr_in32(pdata,
579583
FSL_MC_ERR_SBE) & 0xff0000;
580584

581585
/* set threshold to 1 error per interrupt */
582-
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
586+
ddr_out32(pdata, FSL_MC_ERR_SBE, 0x10000);
583587

584588
/* register interrupts */
585589
pdata->irq = platform_get_irq(op, 0);
@@ -620,12 +624,12 @@ void fsl_mc_err_remove(struct platform_device *op)
620624
edac_dbg(0, "\n");
621625

622626
if (edac_op_state == EDAC_OPSTATE_INT) {
623-
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
627+
ddr_out32(pdata, FSL_MC_ERR_INT_EN, 0);
624628
}
625629

626-
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
630+
ddr_out32(pdata, FSL_MC_ERR_DISABLE,
627631
orig_ddr_err_disable);
628-
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
632+
ddr_out32(pdata, FSL_MC_ERR_SBE, orig_ddr_err_sbe);
629633

630634
edac_mc_del_mc(&op->dev);
631635
edac_mc_free(mci);

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