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pinctrl: samsung: add exynosautov920 pinctrl
Add pinctrl data for ExynosAutov920 SoC. It has a newly applied pinctrl register layer for ExynosAuto series. Pinctrl data for ExynosAutoV920 SoC. - GPA0,GPA1 (10): External wake up interrupt - GPQ0 (2): SPMI (PMIC I/F) - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI Signed-off-by: Jaewon Kim <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
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‎drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

Lines changed: 140 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -726,6 +726,146 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = {
726726
.num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl),
727727
};
728728

729+
/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */
730+
static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = {
731+
EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28),
732+
EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24),
733+
EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"),
734+
};
735+
736+
/* pin banks of exynosautov920 pin-controller 1 (AUD) */
737+
static const struct samsung_pin_bank_data exynosautov920_pin_banks1[] = {
738+
EXYNOSV920_PIN_BANK_EINTG(7, 0x0000, "gpb0", 0x18, 0x24, 0x28),
739+
EXYNOSV920_PIN_BANK_EINTG(6, 0x1000, "gpb1", 0x18, 0x24, 0x28),
740+
EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpb2", 0x18, 0x24, 0x28),
741+
EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpb3", 0x18, 0x24, 0x28),
742+
EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpb4", 0x18, 0x24, 0x28),
743+
EXYNOSV920_PIN_BANK_EINTG(5, 0x5000, "gpb5", 0x18, 0x24, 0x28),
744+
EXYNOSV920_PIN_BANK_EINTG(5, 0x6000, "gpb6", 0x18, 0x24, 0x28),
745+
};
746+
747+
/* pin banks of exynosautov920 pin-controller 2 (HSI0) */
748+
static const struct samsung_pin_bank_data exynosautov920_pin_banks2[] = {
749+
EXYNOSV920_PIN_BANK_EINTG(6, 0x0000, "gph0", 0x18, 0x24, 0x28),
750+
EXYNOSV920_PIN_BANK_EINTG(2, 0x1000, "gph1", 0x18, 0x20, 0x24),
751+
};
752+
753+
/* pin banks of exynosautov920 pin-controller 3 (HSI1) */
754+
static const struct samsung_pin_bank_data exynosautov920_pin_banks3[] = {
755+
EXYNOSV920_PIN_BANK_EINTG(7, 0x000, "gph8", 0x18, 0x24, 0x28),
756+
};
757+
758+
/* pin banks of exynosautov920 pin-controller 4 (HSI2) */
759+
static const struct samsung_pin_bank_data exynosautov920_pin_banks4[] = {
760+
EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gph3", 0x18, 0x24, 0x28),
761+
EXYNOSV920_PIN_BANK_EINTG(7, 0x1000, "gph4", 0x18, 0x24, 0x28),
762+
EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gph5", 0x18, 0x24, 0x28),
763+
EXYNOSV920_PIN_BANK_EINTG(7, 0x3000, "gph6", 0x18, 0x24, 0x28),
764+
};
765+
766+
/* pin banks of exynosautov920 pin-controller 5 (HSI2UFS) */
767+
static const struct samsung_pin_bank_data exynosautov920_pin_banks5[] = {
768+
EXYNOSV920_PIN_BANK_EINTG(4, 0x000, "gph2", 0x18, 0x20, 0x24),
769+
};
770+
771+
/* pin banks of exynosautov920 pin-controller 6 (PERIC0) */
772+
static const struct samsung_pin_bank_data exynosautov920_pin_banks6[] = {
773+
EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp0", 0x18, 0x24, 0x28),
774+
EXYNOSV920_PIN_BANK_EINTG(8, 0x1000, "gpp1", 0x18, 0x24, 0x28),
775+
EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpp2", 0x18, 0x24, 0x28),
776+
EXYNOSV920_PIN_BANK_EINTG(5, 0x3000, "gpg0", 0x18, 0x24, 0x28),
777+
EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpp3", 0x18, 0x24, 0x28),
778+
EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp4", 0x18, 0x20, 0x24),
779+
EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpg2", 0x18, 0x20, 0x24),
780+
EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpg5", 0x18, 0x20, 0x24),
781+
EXYNOSV920_PIN_BANK_EINTG(3, 0x8000, "gpg3", 0x18, 0x20, 0x24),
782+
EXYNOSV920_PIN_BANK_EINTG(5, 0x9000, "gpg4", 0x18, 0x24, 0x28),
783+
};
784+
785+
/* pin banks of exynosautov920 pin-controller 7 (PERIC1) */
786+
static const struct samsung_pin_bank_data exynosautov920_pin_banks7[] = {
787+
EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp5", 0x18, 0x24, 0x28),
788+
EXYNOSV920_PIN_BANK_EINTG(5, 0x1000, "gpp6", 0x18, 0x24, 0x28),
789+
EXYNOSV920_PIN_BANK_EINTG(4, 0x2000, "gpp10", 0x18, 0x20, 0x24),
790+
EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpp7", 0x18, 0x24, 0x28),
791+
EXYNOSV920_PIN_BANK_EINTG(4, 0x4000, "gpp8", 0x18, 0x20, 0x24),
792+
EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp11", 0x18, 0x20, 0x24),
793+
EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpp9", 0x18, 0x20, 0x24),
794+
EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpp12", 0x18, 0x20, 0x24),
795+
EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28),
796+
};
797+
798+
static const struct samsung_retention_data exynosautov920_retention_data __initconst = {
799+
.regs = NULL,
800+
.nr_regs = 0,
801+
.value = 0,
802+
.refcnt = &exynos_shared_retention_refcnt,
803+
.init = exynos_retention_init,
804+
};
805+
806+
static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
807+
{
808+
/* pin-controller instance 0 ALIVE data */
809+
.pin_banks = exynosautov920_pin_banks0,
810+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0),
811+
.eint_wkup_init = exynos_eint_wkup_init,
812+
.suspend = exynos_pinctrl_suspend,
813+
.resume = exynos_pinctrl_resume,
814+
.retention_data = &exynosautov920_retention_data,
815+
}, {
816+
/* pin-controller instance 1 AUD data */
817+
.pin_banks = exynosautov920_pin_banks1,
818+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks1),
819+
}, {
820+
/* pin-controller instance 2 HSI0 data */
821+
.pin_banks = exynosautov920_pin_banks2,
822+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2),
823+
.eint_gpio_init = exynos_eint_gpio_init,
824+
.suspend = exynos_pinctrl_suspend,
825+
.resume = exynos_pinctrl_resume,
826+
}, {
827+
/* pin-controller instance 3 HSI1 data */
828+
.pin_banks = exynosautov920_pin_banks3,
829+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3),
830+
.eint_gpio_init = exynos_eint_gpio_init,
831+
.suspend = exynos_pinctrl_suspend,
832+
.resume = exynos_pinctrl_resume,
833+
}, {
834+
/* pin-controller instance 4 HSI2 data */
835+
.pin_banks = exynosautov920_pin_banks4,
836+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4),
837+
.eint_gpio_init = exynos_eint_gpio_init,
838+
.suspend = exynos_pinctrl_suspend,
839+
.resume = exynos_pinctrl_resume,
840+
}, {
841+
/* pin-controller instance 5 HSI2UFS data */
842+
.pin_banks = exynosautov920_pin_banks5,
843+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5),
844+
.eint_gpio_init = exynos_eint_gpio_init,
845+
.suspend = exynos_pinctrl_suspend,
846+
.resume = exynos_pinctrl_resume,
847+
}, {
848+
/* pin-controller instance 6 PERIC0 data */
849+
.pin_banks = exynosautov920_pin_banks6,
850+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6),
851+
.eint_gpio_init = exynos_eint_gpio_init,
852+
.suspend = exynos_pinctrl_suspend,
853+
.resume = exynos_pinctrl_resume,
854+
}, {
855+
/* pin-controller instance 7 PERIC1 data */
856+
.pin_banks = exynosautov920_pin_banks7,
857+
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7),
858+
.eint_gpio_init = exynos_eint_gpio_init,
859+
.suspend = exynos_pinctrl_suspend,
860+
.resume = exynos_pinctrl_resume,
861+
},
862+
};
863+
864+
const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = {
865+
.ctrl = exynosautov920_pin_ctrl,
866+
.num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl),
867+
};
868+
729869
/*
730870
* Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
731871
* gpio/pin-mux/pinconfig controllers.

‎drivers/pinctrl/samsung/pinctrl-exynos.c

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -281,7 +281,10 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
281281
unsigned int svc, group, pin;
282282
int ret;
283283

284-
svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
284+
if (bank->eint_con_offset)
285+
svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);
286+
else
287+
svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
285288
group = EXYNOS_SVC_GROUP(svc);
286289
pin = svc & EXYNOS_SVC_NUM_MASK;
287290

@@ -490,6 +493,22 @@ static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = {
490493
.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
491494
};
492495

496+
static const struct exynos_irq_chip exynosautov920_wkup_irq_chip __initconst = {
497+
.chip = {
498+
.name = "exynosautov920_wkup_irq_chip",
499+
.irq_unmask = exynos_irq_unmask,
500+
.irq_mask = exynos_irq_mask,
501+
.irq_ack = exynos_irq_ack,
502+
.irq_set_type = exynos_irq_set_type,
503+
.irq_set_wake = exynos_wkup_irq_set_wake,
504+
.irq_request_resources = exynos_irq_request_resources,
505+
.irq_release_resources = exynos_irq_release_resources,
506+
},
507+
.eint_wake_mask_value = &eint_wake_mask_value,
508+
.eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
509+
.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
510+
};
511+
493512
/* list of external wakeup controllers supported */
494513
static const struct of_device_id exynos_wkup_irq_ids[] = {
495514
{ .compatible = "samsung,s5pv210-wakeup-eint",
@@ -502,6 +521,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
502521
.data = &exynos7_wkup_irq_chip },
503522
{ .compatible = "samsung,exynosautov9-wakeup-eint",
504523
.data = &exynos7_wkup_irq_chip },
524+
{ .compatible = "samsung,exynosautov920-wakeup-eint",
525+
.data = &exynosautov920_wkup_irq_chip },
505526
{ }
506527
};
507528

‎drivers/pinctrl/samsung/pinctrl-exynos.h

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@
3131
#define EXYNOS7_WKUP_EMASK_OFFSET 0x900
3232
#define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
3333
#define EXYNOS_SVC_OFFSET 0xB08
34+
#define EXYNOSAUTO_SVC_OFFSET 0xF008
3435

3536
/* helpers to access interrupt service register */
3637
#define EXYNOS_SVC_GROUP_SHIFT 3
@@ -140,6 +141,30 @@
140141
.name = id \
141142
}
142143

144+
#define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \
145+
{ \
146+
.type = &exynos850_bank_type_off, \
147+
.pctl_offset = reg, \
148+
.nr_pins = pins, \
149+
.eint_type = EINT_TYPE_GPIO, \
150+
.eint_con_offset = con_offs, \
151+
.eint_mask_offset = mask_offs, \
152+
.eint_pend_offset = pend_offs, \
153+
.name = id \
154+
}
155+
156+
#define EXYNOSV920_PIN_BANK_EINTW(pins, reg, id, con_offs, mask_offs, pend_offs) \
157+
{ \
158+
.type = &exynos850_bank_type_alive, \
159+
.pctl_offset = reg, \
160+
.nr_pins = pins, \
161+
.eint_type = EINT_TYPE_WKUP, \
162+
.eint_con_offset = con_offs, \
163+
.eint_mask_offset = mask_offs, \
164+
.eint_pend_offset = pend_offs, \
165+
.name = id \
166+
}
167+
143168
/**
144169
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
145170
* generated by the external wakeup interrupt controller.

‎drivers/pinctrl/samsung/pinctrl-samsung.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1324,6 +1324,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
13241324
.data = &exynos850_of_data },
13251325
{ .compatible = "samsung,exynosautov9-pinctrl",
13261326
.data = &exynosautov9_of_data },
1327+
{ .compatible = "samsung,exynosautov920-pinctrl",
1328+
.data = &exynosautov920_of_data },
13271329
{ .compatible = "tesla,fsd-pinctrl",
13281330
.data = &fsd_of_data },
13291331
#endif

‎drivers/pinctrl/samsung/pinctrl-samsung.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -362,6 +362,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
362362
extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
363363
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
364364
extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
365+
extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;
365366
extern const struct samsung_pinctrl_of_match_data fsd_of_data;
366367
extern const struct samsung_pinctrl_of_match_data gs101_of_data;
367368
extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;

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