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phy: exynos5-usbdrd: s/FIELD_PREP_CONST/FIELD_PREP where appropriate
Commit 9b6662a ("phy: exynos5-usbdrd: use GENMASK and FIELD_PREP for Exynos5 PHY registers") added FIELD_PREP_CONST() in many cases where FIELD_PREP() would have been more appropriate. It also switched existing uses of FIELD_PREP() to FIELD_PREP_CONST(). FIELD_PREP() is the preferred macro to use whenever possible while FIELD_PREP_CONST() is meant to be used in constant initialisers. Switch (back) to FIELD_PREP(). Fixes: 7e6c2ff ("phy: exynos5-usbdrd: convert some FIELD_PREP_CONST() to FIELD_PREP()") Signed-off-by: André Draszik <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎drivers/phy/samsung/phy-exynos5-usbdrd.c

Lines changed: 28 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -540,33 +540,32 @@ exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst)
540540

541541
/* Use EXTREFCLK as ref clock */
542542
reg &= ~PHYCLKRST_REFCLKSEL;
543-
reg |= FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL,
544-
PHYCLKRST_REFCLKSEL_EXT_REFCLK);
543+
reg |= FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_EXT_REFCLK);
545544

546545
/* FSEL settings corresponding to reference clock */
547546
reg &= ~(PHYCLKRST_FSEL_PIPE |
548547
PHYCLKRST_MPLL_MULTIPLIER |
549548
PHYCLKRST_SSC_REFCLKSEL);
550549
switch (phy_drd->extrefclk) {
551550
case EXYNOS5_FSEL_50MHZ:
552-
reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x00) |
553-
FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER,
554-
PHYCLKRST_MPLL_MULTIPLIER_50M_REF));
551+
reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x00) |
552+
FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER,
553+
PHYCLKRST_MPLL_MULTIPLIER_50M_REF));
555554
break;
556555
case EXYNOS5_FSEL_24MHZ:
557-
reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x88) |
558-
FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER,
559-
PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF));
556+
reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x88) |
557+
FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER,
558+
PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF));
560559
break;
561560
case EXYNOS5_FSEL_20MHZ:
562-
reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x00) |
563-
FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER,
564-
PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF));
561+
reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x00) |
562+
FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER,
563+
PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF));
565564
break;
566565
case EXYNOS5_FSEL_19MHZ2:
567-
reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x88) |
568-
FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER,
569-
PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF));
566+
reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x88) |
567+
FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER,
568+
PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF));
570569
break;
571570
default:
572571
dev_dbg(phy_drd->dev, "unsupported ref clk\n");
@@ -590,8 +589,7 @@ exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst)
590589
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
591590

592591
reg &= ~PHYCLKRST_REFCLKSEL;
593-
reg |= FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL,
594-
PHYCLKRST_REFCLKSEL_EXT_REFCLK);
592+
reg |= FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_EXT_REFCLK);
595593

596594
reg &= ~(PHYCLKRST_FSEL_UTMI |
597595
PHYCLKRST_MPLL_MULTIPLIER |
@@ -647,8 +645,7 @@ static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
647645
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
648646
/* Set Tx De-Emphasis level */
649647
reg &= ~PHYPARAM1_PCS_TXDEEMPH;
650-
reg |= FIELD_PREP_CONST(PHYPARAM1_PCS_TXDEEMPH,
651-
PHYPARAM1_PCS_TXDEEMPH_VAL);
648+
reg |= FIELD_PREP(PHYPARAM1_PCS_TXDEEMPH, PHYPARAM1_PCS_TXDEEMPH_VAL);
652649
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
653650

654651
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
@@ -669,7 +666,7 @@ exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready(struct exynos5_usbdrd_phy *phy_drd)
669666

670667
reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL);
671668
reg &= ~SECPMACTL_PMA_REF_FREQ_SEL;
672-
reg |= FIELD_PREP_CONST(SECPMACTL_PMA_REF_FREQ_SEL, 1);
669+
reg |= FIELD_PREP(SECPMACTL_PMA_REF_FREQ_SEL, 1);
673670
/* SFR reset */
674671
reg |= (SECPMACTL_PMA_LOW_PWR | SECPMACTL_PMA_APB_SW_RST);
675672
reg &= ~(SECPMACTL_PMA_ROPLL_REF_CLK_SEL |
@@ -799,15 +796,13 @@ static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
799796
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
800797
/* Set Loss-of-Signal Detector sensitivity */
801798
reg &= ~PHYPARAM0_REF_LOSLEVEL;
802-
reg |= FIELD_PREP_CONST(PHYPARAM0_REF_LOSLEVEL,
803-
PHYPARAM0_REF_LOSLEVEL_VAL);
799+
reg |= FIELD_PREP(PHYPARAM0_REF_LOSLEVEL, PHYPARAM0_REF_LOSLEVEL_VAL);
804800
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
805801

806802
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
807803
/* Set Tx De-Emphasis level */
808804
reg &= ~PHYPARAM1_PCS_TXDEEMPH;
809-
reg |= FIELD_PREP_CONST(PHYPARAM1_PCS_TXDEEMPH,
810-
PHYPARAM1_PCS_TXDEEMPH_VAL);
805+
reg |= FIELD_PREP(PHYPARAM1_PCS_TXDEEMPH, PHYPARAM1_PCS_TXDEEMPH_VAL);
811806
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
812807

813808
/* UTMI Power Control */
@@ -838,7 +833,7 @@ static int exynos5_usbdrd_phy_init(struct phy *phy)
838833
* See xHCI 1.0 spec, 5.2.4
839834
*/
840835
reg = LINKSYSTEM_XHCI_VERSION_CONTROL |
841-
FIELD_PREP_CONST(LINKSYSTEM_FLADJ, 0x20);
836+
FIELD_PREP(LINKSYSTEM_FLADJ, 0x20);
842837
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
843838

844839
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
@@ -1145,8 +1140,7 @@ static void exynos7870_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
11451140
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
11461141
/* Use PADREFCLK as ref clock */
11471142
reg &= ~PHYCLKRST_REFCLKSEL;
1148-
reg |= FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL,
1149-
PHYCLKRST_REFCLKSEL_PAD_REFCLK);
1143+
reg |= FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_PAD_REFCLK);
11501144
/* Select ref clock rate */
11511145
reg &= ~PHYCLKRST_FSEL_UTMI;
11521146
reg &= ~PHYCLKRST_FSEL_PIPE;
@@ -1169,7 +1163,7 @@ static void exynos7870_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
11691163
else
11701164
reg &= ~HSPHYPLLTUNE_PLL_B_TUNE;
11711165
reg &= ~HSPHYPLLTUNE_PLL_P_TUNE;
1172-
reg |= FIELD_PREP_CONST(HSPHYPLLTUNE_PLL_P_TUNE, 14);
1166+
reg |= FIELD_PREP(HSPHYPLLTUNE_PLL_P_TUNE, 14);
11731167
writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYPLLTUNE);
11741168

11751169
/* High-Speed PHY control */
@@ -1187,7 +1181,7 @@ static void exynos7870_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
11871181
*/
11881182
reg |= LINKSYSTEM_XHCI_VERSION_CONTROL;
11891183
reg &= ~LINKSYSTEM_FLADJ;
1190-
reg |= FIELD_PREP_CONST(LINKSYSTEM_FLADJ, 0x20);
1184+
reg |= FIELD_PREP(LINKSYSTEM_FLADJ, 0x20);
11911185
/* Set VBUSVALID signal as the VBUS pad is not used */
11921186
reg |= LINKSYSTEM_FORCE_BVALID;
11931187
reg |= LINKSYSTEM_FORCE_VBUSVALID;
@@ -1350,7 +1344,7 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
13501344

13511345
/* Set VBUS Valid and D+ pull-up control by VBUS pad usage */
13521346
reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
1353-
reg |= FIELD_PREP_CONST(LINKCTRL_BUS_FILTER_BYPASS, 0xf);
1347+
reg |= FIELD_PREP(LINKCTRL_BUS_FILTER_BYPASS, 0xf);
13541348
writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
13551349

13561350
if (!phy_drd->sw) {
@@ -1367,19 +1361,19 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
13671361
reg &= ~SSPPLLCTL_FSEL;
13681362
switch (phy_drd->extrefclk) {
13691363
case EXYNOS5_FSEL_50MHZ:
1370-
reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7);
1364+
reg |= FIELD_PREP(SSPPLLCTL_FSEL, 7);
13711365
break;
13721366
case EXYNOS5_FSEL_26MHZ:
1373-
reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6);
1367+
reg |= FIELD_PREP(SSPPLLCTL_FSEL, 6);
13741368
break;
13751369
case EXYNOS5_FSEL_24MHZ:
1376-
reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2);
1370+
reg |= FIELD_PREP(SSPPLLCTL_FSEL, 2);
13771371
break;
13781372
case EXYNOS5_FSEL_20MHZ:
1379-
reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1);
1373+
reg |= FIELD_PREP(SSPPLLCTL_FSEL, 1);
13801374
break;
13811375
case EXYNOS5_FSEL_19MHZ2:
1382-
reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0);
1376+
reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0);
13831377
break;
13841378
default:
13851379
dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n",

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