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Merge tag 'drm-intel-next-2024-08-29' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
Cross-driver (xe-core) Changes: - Require BMG scanout buffers to be 64k physically aligned (Maarten) Core (drm) Changes: - Introducing Xe2 ccs modifiers for integrated and discrete graphics (Juha-Pekka) Driver Changes: - General cleanup and more work moving towards intel_display isolation (Jani) - New display workaround (Suraj) - Use correct cp_irq_count on HDCP (Suraj) - eDP PSR fix when CRC is enabled (Jouni) - Fix DP MST state after a sink reset (Imre) - Fix Arrow Lake GSC firmware version (John) - Use chained DSBs for LUT programming (Ville) Signed-off-by: Dave Airlie <[email protected]> From: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 8bdb468 + b5d4657 commit 6d0ebb3

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80 files changed

+1515
-775
lines changed

‎drivers/gpu/drm/i915/display/intel_alpm.c‎

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -139,7 +139,7 @@ static int
139139
_lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
140140
const struct intel_crtc_state *crtc_state)
141141
{
142-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
142+
struct intel_display *display = to_intel_display(intel_dp);
143143
int aux_less_wake_time, aux_less_wake_lines, silence_period,
144144
lfps_half_cycle;
145145

@@ -158,7 +158,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
158158
lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)
159159
return false;
160160

161-
if (i915->display.params.psr_safest_params)
161+
if (display->params.psr_safest_params)
162162
aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;
163163

164164
intel_dp->alpm_parameters.aux_less_wake_lines = aux_less_wake_lines;
@@ -171,10 +171,10 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
171171
static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
172172
const struct intel_crtc_state *crtc_state)
173173
{
174-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
174+
struct intel_display *display = to_intel_display(intel_dp);
175175
int check_entry_lines;
176176

177-
if (DISPLAY_VER(i915) < 20)
177+
if (DISPLAY_VER(display) < 20)
178178
return true;
179179

180180
/* ALPM Entry Check = 2 + CEILING( 5us /tline ) */
@@ -187,7 +187,7 @@ static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
187187
if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))
188188
return false;
189189

190-
if (i915->display.params.psr_safest_params)
190+
if (display->params.psr_safest_params)
191191
check_entry_lines = 15;
192192

193193
intel_dp->alpm_parameters.check_entry_lines = check_entry_lines;
@@ -212,9 +212,9 @@ static int tgl_io_buffer_wake_time(void)
212212

213213
static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state)
214214
{
215-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
215+
struct intel_display *display = to_intel_display(crtc_state);
216216

217-
if (DISPLAY_VER(i915) >= 12)
217+
if (DISPLAY_VER(display) >= 12)
218218
return tgl_io_buffer_wake_time();
219219
else
220220
return skl_io_buffer_wake_time();
@@ -223,7 +223,7 @@ static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state)
223223
bool intel_alpm_compute_params(struct intel_dp *intel_dp,
224224
const struct intel_crtc_state *crtc_state)
225225
{
226-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
226+
struct intel_display *display = to_intel_display(intel_dp);
227227
int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time;
228228
int tfw_exit_latency = 20; /* eDP spec */
229229
int phy_wake = 4; /* eDP spec */
@@ -236,9 +236,9 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp,
236236
fast_wake_time = precharge + preamble + phy_wake +
237237
tfw_exit_latency;
238238

239-
if (DISPLAY_VER(i915) >= 20)
239+
if (DISPLAY_VER(display) >= 20)
240240
max_wake_lines = 68;
241-
else if (DISPLAY_VER(i915) >= 12)
241+
else if (DISPLAY_VER(display) >= 12)
242242
max_wake_lines = 12;
243243
else
244244
max_wake_lines = 8;
@@ -255,7 +255,7 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp,
255255
if (!_lnl_compute_alpm_params(intel_dp, crtc_state))
256256
return false;
257257

258-
if (i915->display.params.psr_safest_params)
258+
if (display->params.psr_safest_params)
259259
io_wake_lines = fast_wake_lines = max_wake_lines;
260260

261261
/* According to Bspec lower limit should be set as 7 lines. */
@@ -269,15 +269,15 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
269269
struct intel_crtc_state *crtc_state,
270270
struct drm_connector_state *conn_state)
271271
{
272-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
272+
struct intel_display *display = to_intel_display(intel_dp);
273273
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
274274
int waketime_in_lines, first_sdp_position;
275275
int context_latency, guardband;
276276

277277
if (!intel_dp_is_edp(intel_dp))
278278
return;
279279

280-
if (DISPLAY_VER(i915) < 20)
280+
if (DISPLAY_VER(display) < 20)
281281
return;
282282

283283
if (!intel_dp->as_sdp_supported)
@@ -309,13 +309,13 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
309309
static void lnl_alpm_configure(struct intel_dp *intel_dp,
310310
const struct intel_crtc_state *crtc_state)
311311
{
312-
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
312+
struct intel_display *display = to_intel_display(intel_dp);
313313
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
314314
enum port port = dp_to_dig_port(intel_dp)->base.port;
315315
u32 alpm_ctl;
316316

317-
if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled &&
318-
!intel_dp_is_edp(intel_dp)))
317+
if (DISPLAY_VER(display) < 20 ||
318+
(!intel_dp->psr.sel_update_enabled && !intel_dp_is_edp(intel_dp)))
319319
return;
320320

321321
/*
@@ -329,16 +329,16 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
329329
ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
330330
ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines);
331331

332-
intel_de_write(dev_priv,
333-
PORT_ALPM_CTL(dev_priv, port),
332+
intel_de_write(display,
333+
PORT_ALPM_CTL(display, port),
334334
PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
335335
PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
336336
PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
337337
PORT_ALPM_CTL_SILENCE_PERIOD(
338338
intel_dp->alpm_parameters.silence_period_sym_clocks));
339339

340-
intel_de_write(dev_priv,
341-
PORT_ALPM_LFPS_CTL(dev_priv, port),
340+
intel_de_write(display,
341+
PORT_ALPM_LFPS_CTL(display, port),
342342
PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
343343
PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
344344
intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
@@ -356,7 +356,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
356356

357357
alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines);
358358

359-
intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl);
359+
intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
360360
}
361361

362362
void intel_alpm_configure(struct intel_dp *intel_dp,
@@ -368,14 +368,14 @@ void intel_alpm_configure(struct intel_dp *intel_dp,
368368
static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
369369
{
370370
struct intel_connector *connector = m->private;
371-
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
371+
struct intel_display *display = to_intel_display(connector);
372372
struct drm_crtc *crtc;
373373
struct intel_crtc_state *crtc_state;
374374
enum transcoder cpu_transcoder;
375375
u32 alpm_ctl;
376376
int ret;
377377

378-
ret = drm_modeset_lock_single_interruptible(&dev_priv->drm.mode_config.connection_mutex);
378+
ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
379379
if (ret)
380380
return ret;
381381

@@ -387,14 +387,14 @@ static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
387387

388388
crtc_state = to_intel_crtc_state(crtc->state);
389389
cpu_transcoder = crtc_state->cpu_transcoder;
390-
alpm_ctl = intel_de_read(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder));
390+
alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));
391391
seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl & ALPM_CTL_LOBF_ENABLE));
392392
seq_printf(m, "Aux-wake alpm status: %s\n",
393393
str_enabled_disabled(!(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE)));
394394
seq_printf(m, "Aux-less alpm status: %s\n",
395395
str_enabled_disabled(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE));
396396
out:
397-
drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex);
397+
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
398398

399399
return ret;
400400
}
@@ -403,10 +403,10 @@ DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info);
403403

404404
void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
405405
{
406-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
406+
struct intel_display *display = to_intel_display(connector);
407407
struct dentry *root = connector->base.debugfs_entry;
408408

409-
if (DISPLAY_VER(i915) < 20 ||
409+
if (DISPLAY_VER(display) < 20 ||
410410
connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
411411
return;
412412

‎drivers/gpu/drm/i915/display/intel_atomic.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -276,7 +276,8 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
276276
crtc_state->do_async_flip = false;
277277
crtc_state->fb_bits = 0;
278278
crtc_state->update_planes = 0;
279-
crtc_state->dsb = NULL;
279+
crtc_state->dsb_color_vblank = NULL;
280+
crtc_state->dsb_color_commit = NULL;
280281

281282
return &crtc_state->uapi;
282283
}
@@ -310,7 +311,8 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
310311
{
311312
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
312313

313-
drm_WARN_ON(crtc->dev, crtc_state->dsb);
314+
drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank);
315+
drm_WARN_ON(crtc->dev, crtc_state->dsb_color_commit);
314316

315317
__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
316318
intel_crtc_free_hw_state(crtc_state);

‎drivers/gpu/drm/i915/display/intel_backlight.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1011,7 +1011,7 @@ static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
10111011
{
10121012
struct drm_i915_private *i915 = to_i915(connector->base.dev);
10131013

1014-
return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
1014+
return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
10151015
pwm_freq_hz);
10161016
}
10171017

@@ -1073,7 +1073,7 @@ static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
10731073
{
10741074
struct drm_i915_private *i915 = to_i915(connector->base.dev);
10751075

1076-
return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
1076+
return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
10771077
pwm_freq_hz * 128);
10781078
}
10791079

@@ -1091,7 +1091,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
10911091
int clock;
10921092

10931093
if (IS_PINEVIEW(i915))
1094-
clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
1094+
clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
10951095
else
10961096
clock = KHz(i915->display.cdclk.hw.cdclk);
10971097

@@ -1109,7 +1109,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
11091109
int clock;
11101110

11111111
if (IS_G4X(i915))
1112-
clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
1112+
clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
11131113
else
11141114
clock = KHz(i915->display.cdclk.hw.cdclk);
11151115

@@ -1133,7 +1133,7 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
11331133
clock = MHz(25);
11341134
mul = 16;
11351135
} else {
1136-
clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
1136+
clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
11371137
mul = 128;
11381138
}
11391139

‎drivers/gpu/drm/i915/display/intel_color.c‎

Lines changed: 37 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1313,8 +1313,8 @@ static void ilk_lut_write(const struct intel_crtc_state *crtc_state,
13131313
{
13141314
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
13151315

1316-
if (crtc_state->dsb)
1317-
intel_dsb_reg_write(crtc_state->dsb, reg, val);
1316+
if (crtc_state->dsb_color_vblank)
1317+
intel_dsb_reg_write(crtc_state->dsb_color_vblank, reg, val);
13181318
else
13191319
intel_de_write_fw(i915, reg, val);
13201320
}
@@ -1337,15 +1337,15 @@ static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state,
13371337
* unless we either write each entry twice,
13381338
* or use non-posted writes
13391339
*/
1340-
if (crtc_state->dsb)
1341-
intel_dsb_nonpost_start(crtc_state->dsb);
1340+
if (crtc_state->dsb_color_vblank)
1341+
intel_dsb_nonpost_start(crtc_state->dsb_color_vblank);
13421342

13431343
for (i = 0; i < 256; i++)
13441344
ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
13451345
i9xx_lut_8(&lut[i]));
13461346

1347-
if (crtc_state->dsb)
1348-
intel_dsb_nonpost_end(crtc_state->dsb);
1347+
if (crtc_state->dsb_color_vblank)
1348+
intel_dsb_nonpost_end(crtc_state->dsb_color_vblank);
13491349
}
13501350

13511351
static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,
@@ -1870,7 +1870,7 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
18701870
{
18711871
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
18721872

1873-
if (crtc_state->dsb)
1873+
if (crtc_state->dsb_color_vblank)
18741874
return;
18751875

18761876
i915->display.funcs.color->load_luts(crtc_state);
@@ -1890,8 +1890,8 @@ void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
18901890

18911891
i915->display.funcs.color->color_commit_arm(crtc_state);
18921892

1893-
if (crtc_state->dsb)
1894-
intel_dsb_commit(crtc_state->dsb, true);
1893+
if (crtc_state->dsb_color_commit)
1894+
intel_dsb_commit(crtc_state->dsb_color_commit, false);
18951895
}
18961896

18971897
void intel_color_post_update(const struct intel_crtc_state *crtc_state)
@@ -1919,33 +1919,51 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
19191919
if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
19201920
return;
19211921

1922-
crtc_state->dsb = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024);
1923-
if (!crtc_state->dsb)
1922+
crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);
1923+
if (!crtc_state->dsb_color_vblank)
19241924
return;
19251925

19261926
i915->display.funcs.color->load_luts(crtc_state);
19271927

1928-
intel_dsb_finish(crtc_state->dsb);
1928+
intel_dsb_finish(crtc_state->dsb_color_vblank);
1929+
1930+
crtc_state->dsb_color_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 16);
1931+
if (!crtc_state->dsb_color_commit) {
1932+
intel_dsb_cleanup(crtc_state->dsb_color_vblank);
1933+
crtc_state->dsb_color_vblank = NULL;
1934+
return;
1935+
}
1936+
1937+
intel_dsb_chain(state, crtc_state->dsb_color_commit,
1938+
crtc_state->dsb_color_vblank, true);
1939+
1940+
intel_dsb_finish(crtc_state->dsb_color_commit);
19291941
}
19301942

19311943
void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
19321944
{
1933-
if (!crtc_state->dsb)
1934-
return;
1945+
if (crtc_state->dsb_color_commit) {
1946+
intel_dsb_cleanup(crtc_state->dsb_color_commit);
1947+
crtc_state->dsb_color_commit = NULL;
1948+
}
19351949

1936-
intel_dsb_cleanup(crtc_state->dsb);
1937-
crtc_state->dsb = NULL;
1950+
if (crtc_state->dsb_color_vblank) {
1951+
intel_dsb_cleanup(crtc_state->dsb_color_vblank);
1952+
crtc_state->dsb_color_vblank = NULL;
1953+
}
19381954
}
19391955

19401956
void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)
19411957
{
1942-
if (crtc_state->dsb)
1943-
intel_dsb_wait(crtc_state->dsb);
1958+
if (crtc_state->dsb_color_commit)
1959+
intel_dsb_wait(crtc_state->dsb_color_commit);
1960+
if (crtc_state->dsb_color_vblank)
1961+
intel_dsb_wait(crtc_state->dsb_color_vblank);
19441962
}
19451963

19461964
bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state)
19471965
{
1948-
return crtc_state->dsb;
1966+
return crtc_state->dsb_color_vblank;
19491967
}
19501968

19511969
static bool intel_can_preload_luts(struct intel_atomic_state *state,

‎drivers/gpu/drm/i915/display/intel_ddi.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4900,7 +4900,7 @@ void intel_ddi_init(struct intel_display *display,
49004900
* driver. In that case we should skip initializing the corresponding
49014901
* outputs.
49024902
*/
4903-
if (intel_hti_uses_phy(dev_priv, phy)) {
4903+
if (intel_hti_uses_phy(display, phy)) {
49044904
drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
49054905
port_name(port), phy_name(phy));
49064906
return;

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