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Ranjan Kumarmartinkpetersen
Ranjan Kumar
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martinkpetersen
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scsi: mpi3mr: Update MPI Headers to revision 34
Update MPI Headers to revision 34. Signed-off-by: Prayas Patel <[email protected]> Signed-off-by: Ranjan Kumar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Martin K. Petersen <[email protected]>
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‎drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h

Lines changed: 31 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@
6767
#define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000ff00)
6868
#define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT (8)
6969
#define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000ff)
70+
#define MPI3_INSTANCE_PGAD_INSTANCE_MASK (0x0000ffff)
7071
struct mpi3_config_request {
7172
__le16 host_tag;
7273
u8 ioc_use_only02;
@@ -75,7 +76,8 @@ struct mpi3_config_request {
7576
u8 ioc_use_only06;
7677
u8 msg_flags;
7778
__le16 change_count;
78-
__le16 reserved0a;
79+
u8 proxy_ioc_number;
80+
u8 reserved0b;
7981
u8 page_version;
8082
u8 page_number;
8183
u8 page_type;
@@ -206,6 +208,9 @@ struct mpi3_config_page_header {
206208
#define MPI3_MFGPAGE_DEVID_SAS5116_MPI_MGMT (0x00b5)
207209
#define MPI3_MFGPAGE_DEVID_SAS5116_NVME_MGMT (0x00b6)
208210
#define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH (0x00b8)
211+
#define MPI3_MFGPAGE_DEVID_SAS5248_MPI (0x00f0)
212+
#define MPI3_MFGPAGE_DEVID_SAS5248_MPI_NS (0x00f1)
213+
#define MPI3_MFGPAGE_DEVID_SAS5248_PCIE_SWITCH (0x00f2)
209214
struct mpi3_man_page0 {
210215
struct mpi3_config_page_header header;
211216
u8 chip_revision[8];
@@ -1074,6 +1079,8 @@ struct mpi3_io_unit_page8 {
10741079
#define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING (0x04)
10751080
#define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02)
10761081
#define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01)
1082+
#define MPI3_IOUNIT8_SBMODE_CURRENT_KEY_IOUNIT17 (0x10)
1083+
#define MPI3_IOUNIT8_SBMODE_HARD_SECURE_RECERTIFIED (0x08)
10771084
struct mpi3_io_unit_page9 {
10781085
struct mpi3_config_page_header header;
10791086
__le32 flags;
@@ -1089,6 +1096,8 @@ struct mpi3_io_unit_page9 {
10891096
#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE (0x00000004)
10901097
#define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x00000001)
10911098
#define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xffff)
1099+
#define MPI3_IOUNIT9_FIRSTDEVICE_IN_DRIVER_PAGE_0 (0xfffe)
1100+
10921101
struct mpi3_io_unit_page10 {
10931102
struct mpi3_config_page_header header;
10941103
u8 flags;
@@ -1224,6 +1233,19 @@ struct mpi3_io_unit_page15 {
12241233
#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO (0x01)
12251234
#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO (0x02)
12261235
#define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED (0x00)
1236+
1237+
struct mpi3_io_unit_page17 {
1238+
struct mpi3_config_page_header header;
1239+
u8 num_instances;
1240+
u8 instance;
1241+
__le16 reserved0a;
1242+
__le32 reserved0c[4];
1243+
__le16 key_length;
1244+
u8 encryption_algorithm;
1245+
u8 reserved1f;
1246+
__le32 current_key[];
1247+
};
1248+
#define MPI3_IOUNIT17_PAGEVERSION (0x00)
12271249
struct mpi3_ioc_page0 {
12281250
struct mpi3_config_page_header header;
12291251
__le32 reserved08;
@@ -1311,7 +1333,7 @@ struct mpi3_driver_page0 {
13111333
u8 tur_interval;
13121334
u8 reserved10;
13131335
u8 security_key_timeout;
1314-
__le16 reserved12;
1336+
__le16 first_device;
13151337
__le32 reserved14;
13161338
__le32 reserved18;
13171339
};
@@ -1324,11 +1346,13 @@ struct mpi3_driver_page0 {
13241346
#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000)
13251347
#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001)
13261348
#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS (0x00000002)
1349+
#define MPI3_DRIVER0_FIRSTDEVICE_IGNORE1 (0x0000)
1350+
#define MPI3_DRIVER0_FIRSTDEVICE_IGNORE2 (0xffff)
13271351
struct mpi3_driver_page1 {
13281352
struct mpi3_config_page_header header;
13291353
__le32 flags;
13301354
u8 time_stamp_update;
1331-
__le32 reserved0c;
1355+
u8 reserved0d[3];
13321356
__le16 host_diag_trace_max_size;
13331357
__le16 host_diag_trace_min_size;
13341358
__le16 host_diag_trace_decrement_size;
@@ -2348,6 +2372,10 @@ struct mpi3_device0_vd_format {
23482372
#define MPI3_DEVICE0_VD_DEVICE_INFO_SAS (0x0001)
23492373
#define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK (0xf000)
23502374
#define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT (12)
2375+
#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_MASK (0x0003)
2376+
#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_HDD (0x0000)
2377+
#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_SSD (0x0001)
2378+
#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_NO_GUIDANCE (0x0002)
23512379
union mpi3_device0_dev_spec_format {
23522380
struct mpi3_device0_sas_sata_format sas_sata_format;
23532381
struct mpi3_device0_pcie_format pcie_format;

‎drivers/scsi/mpi3mr/mpi/mpi30_image.h

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -205,13 +205,14 @@ struct mpi3_encrypted_hash_entry {
205205
u8 hash_image_type;
206206
u8 hash_algorithm;
207207
u8 encryption_algorithm;
208-
u8 reserved03;
208+
u8 flags;
209209
__le16 public_key_size;
210210
__le16 signature_size;
211211
__le32 public_key[MPI3_PUBLIC_KEY_MAX];
212212
};
213-
214-
#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_SIGNATURE (0x03)
213+
#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_HASH (0x03)
214+
#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_HASH_1_OF_2 (0x04)
215+
#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_HASH_2_OF_2 (0x05)
215216
#define MPI3_HASH_ALGORITHM_VERSION_MASK (0xe0)
216217
#define MPI3_HASH_ALGORITHM_VERSION_NONE (0x00)
217218
#define MPI3_HASH_ALGORITHM_VERSION_SHA1 (0x20)
@@ -230,6 +231,12 @@ struct mpi3_encrypted_hash_entry {
230231
#define MPI3_ENCRYPTION_ALGORITHM_RSA4096 (0x05)
231232
#define MPI3_ENCRYPTION_ALGORITHM_RSA3072 (0x06)
232233

234+
/* hierarchical signature system (hss) */
235+
#define MPI3_ENCRYPTION_ALGORITHM_ML_DSA_87 (0x0b)
236+
#define MPI3_ENCRYPTION_ALGORITHM_ML_DSA_65 (0x0c)
237+
#define MPI3_ENCRYPTION_ALGORITHM_ML_DSA_44 (0x0d)
238+
#define MPI3_ENCRYPTED_HASH_ENTRY_FLAGS_PAIRED_KEY_MASK (0x0f)
239+
233240
#ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX
234241
#define MPI3_ENCRYPTED_HASH_ENTRY_MAX (1)
235242
#endif

‎drivers/scsi/mpi3mr/mpi/mpi30_ioc.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,12 @@ struct mpi3_ioc_init_request {
3939
#define MPI3_WHOINIT_HOST_DRIVER (0x03)
4040
#define MPI3_WHOINIT_MANUFACTURER (0x04)
4141

42+
#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_MASK (0x00000003)
43+
#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_GUIDANCE (0x00000000)
44+
#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_SPECIAL (0x00000001)
45+
#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_HDD (0x00000002)
46+
#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_SSD (0x00000003)
47+
4248
struct mpi3_ioc_facts_request {
4349
__le16 host_tag;
4450
u8 ioc_use_only02;
@@ -140,6 +146,8 @@ struct mpi3_ioc_facts_data {
140146
#define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020)
141147
#define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0010)
142148
#define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0008)
149+
#define MPI3_IOCFACTS_EXCEPT_BLOCKING_BOOT_EVENT (0x0004)
150+
#define MPI3_IOCFACTS_EXCEPT_SECURITY_SELFTEST_FAILURE (0x0002)
143151
#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001)
144152
#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000)
145153
#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001)

‎drivers/scsi/mpi3mr/mpi/mpi30_transport.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ union mpi3_version_union {
1818

1919
#define MPI3_VERSION_MAJOR (3)
2020
#define MPI3_VERSION_MINOR (0)
21-
#define MPI3_VERSION_UNIT (31)
21+
#define MPI3_VERSION_UNIT (34)
2222
#define MPI3_VERSION_DEV (0)
2323
#define MPI3_DEVHANDLE_INVALID (0xffff)
2424
struct mpi3_sysif_oper_queue_indexes {
@@ -158,6 +158,7 @@ struct mpi3_sysif_registers {
158158
#define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_NEEDED (0x0000f004)
159159
#define MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED (0x0000f005)
160160
#define MPI3_SYSIF_FAULT_CODE_TEMP_THRESHOLD_EXCEEDED (0x0000f006)
161+
#define MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER (0x0000f007)
161162
#define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001c14)
162163
#define MPI3_SYSIF_FAULT_INFO1_OFFSET (0x00001c18)
163164
#define MPI3_SYSIF_FAULT_INFO2_OFFSET (0x00001c1c)
@@ -410,6 +411,7 @@ struct mpi3_default_reply {
410411
#define MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
411412
#define MPI3_IOCSTATUS_INVALID_FIELD (0x0007)
412413
#define MPI3_IOCSTATUS_INVALID_STATE (0x0008)
414+
#define MPI3_IOCSTATUS_SHUTDOWN_ACTIVE (0x0009)
413415
#define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000a)
414416
#define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000b)
415417
#define MPI3_IOCSTATUS_ALLOWED_CMD_BLOCK (0x000c)

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