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37 | 37 | #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
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38 | 38 | #define AST_IO_VGACRCB_HWC_ENABLED BIT(1)
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39 | 39 |
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40 |
| -#define AST_IO_VGACRD1_MCU_FW_EXECUTING BIT(5) |
| 40 | +#define AST_IO_VGACRD1_MCU_FW_EXECUTING BIT(5) |
| 41 | +/* Display Transmitter Type */ |
| 42 | +#define AST_IO_VGACRD1_TX_TYPE_MASK GENMASK(3, 1) |
| 43 | +#define AST_IO_VGACRD1_NO_TX 0x00 |
| 44 | +#define AST_IO_VGACRD1_TX_ITE66121_VBIOS 0x02 |
| 45 | +#define AST_IO_VGACRD1_TX_SIL164_VBIOS 0x04 |
| 46 | +#define AST_IO_VGACRD1_TX_CH7003_VBIOS 0x06 |
| 47 | +#define AST_IO_VGACRD1_TX_DP501_VBIOS 0x08 |
| 48 | +#define AST_IO_VGACRD1_TX_ANX9807_VBIOS 0x0a |
| 49 | +#define AST_IO_VGACRD1_TX_FW_EMBEDDED_FW 0x0c |
| 50 | +#define AST_IO_VGACRD1_TX_ASTDP 0x0e |
| 51 | + |
41 | 52 | #define AST_IO_VGACRD7_EDID_VALID_FLAG BIT(0)
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42 | 53 | #define AST_IO_VGACRDC_LINK_SUCCESS BIT(0)
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43 | 54 | #define AST_IO_VGACRDF_HPD BIT(0)
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49 | 60 | #define AST_IO_VGAIR1_R (0x5A)
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50 | 61 | #define AST_IO_VGAIR1_VREFRESH BIT(3)
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51 | 62 |
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52 |
| -/* |
53 |
| - * Display Transmitter Type |
54 |
| - */ |
55 |
| - |
56 |
| -#define TX_TYPE_MASK GENMASK(3, 1) |
57 |
| -#define NO_TX (0 << 1) |
58 |
| -#define ITE66121_VBIOS_TX (1 << 1) |
59 |
| -#define SI164_VBIOS_TX (2 << 1) |
60 |
| -#define CH7003_VBIOS_TX (3 << 1) |
61 |
| -#define DP501_VBIOS_TX (4 << 1) |
62 |
| -#define ANX9807_VBIOS_TX (5 << 1) |
63 |
| -#define TX_FW_EMBEDDED_FW_TX (6 << 1) |
64 |
| -#define ASTDP_DPMCU_TX (7 << 1) |
65 | 63 |
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66 | 64 | #define AST_VRAM_INIT_STATUS_MASK GENMASK(7, 6)
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67 | 65 | //#define AST_VRAM_INIT_BY_BMC BIT(7)
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