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airliedairlied
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Merge tag 'mediatek-drm-next-5.6' of https://github.com/ckhu-mediatek/linux.git-tags into drm-next
Mediatek DRM Next for Linux 5.6 This fix non-smooth cursor problem, add cmdq support, add ctm property support and some refinement. Signed-off-by: Dave Airlie <[email protected]> From: CK Hu <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/1578972526.14594.8.camel@mtksdaap41
2 parents fd7226f + d04a07a commit 6fc376f

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15 files changed

+666
-261
lines changed

15 files changed

+666
-261
lines changed

‎drivers/gpu/drm/mediatek/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
2020
mediatek-drm-hdmi-objs := mtk_cec.o \
2121
mtk_hdmi.o \
2222
mtk_hdmi_ddc.o \
23-
mtk_mt2701_hdmi_phy.o \
23+
mtk_mt2701_hdmi_phy.o \
2424
mtk_mt8173_hdmi_phy.o \
2525
mtk_hdmi_phy.o
2626

‎drivers/gpu/drm/mediatek/mtk_disp_color.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include <linux/of_device.h>
1010
#include <linux/of_irq.h>
1111
#include <linux/platform_device.h>
12+
#include <linux/soc/mediatek/mtk-cmdq.h>
1213

1314
#include "mtk_drm_crtc.h"
1415
#include "mtk_drm_ddp_comp.h"
@@ -45,12 +46,12 @@ static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp)
4546

4647
static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
4748
unsigned int h, unsigned int vrefresh,
48-
unsigned int bpc)
49+
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
4950
{
5051
struct mtk_disp_color *color = comp_to_color(comp);
5152

52-
writel(w, comp->regs + DISP_COLOR_WIDTH(color));
53-
writel(h, comp->regs + DISP_COLOR_HEIGHT(color));
53+
mtk_ddp_write(cmdq_pkt, w, comp, DISP_COLOR_WIDTH(color));
54+
mtk_ddp_write(cmdq_pkt, h, comp, DISP_COLOR_HEIGHT(color));
5455
}
5556

5657
static void mtk_color_start(struct mtk_ddp_comp *comp)

‎drivers/gpu/drm/mediatek/mtk_disp_ovl.c

Lines changed: 40 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include <linux/of_device.h>
1212
#include <linux/of_irq.h>
1313
#include <linux/platform_device.h>
14+
#include <linux/soc/mediatek/mtk-cmdq.h>
1415

1516
#include "mtk_drm_crtc.h"
1617
#include "mtk_drm_ddp_comp.h"
@@ -124,14 +125,15 @@ static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
124125

125126
static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
126127
unsigned int h, unsigned int vrefresh,
127-
unsigned int bpc)
128+
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
128129
{
129130
if (w != 0 && h != 0)
130-
writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE);
131-
writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR);
131+
mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp,
132+
DISP_REG_OVL_ROI_SIZE);
133+
mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR);
132134

133-
writel(0x1, comp->regs + DISP_REG_OVL_RST);
134-
writel(0x0, comp->regs + DISP_REG_OVL_RST);
135+
mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST);
136+
mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST);
135137
}
136138

137139
static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
@@ -175,16 +177,16 @@ static int mtk_ovl_layer_check(struct mtk_ddp_comp *comp, unsigned int idx,
175177
return 0;
176178
}
177179

178-
static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
180+
static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx,
181+
struct cmdq_pkt *cmdq_pkt)
179182
{
180-
unsigned int reg;
181183
unsigned int gmc_thrshd_l;
182184
unsigned int gmc_thrshd_h;
183185
unsigned int gmc_value;
184186
struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
185187

186-
writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
187-
188+
mtk_ddp_write(cmdq_pkt, 0x1, comp,
189+
DISP_REG_OVL_RDMA_CTRL(idx));
188190
gmc_thrshd_l = GMC_THRESHOLD_LOW >>
189191
(GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
190192
gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
@@ -194,22 +196,19 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
194196
else
195197
gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
196198
gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
197-
writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
198-
199-
reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
200-
reg = reg | BIT(idx);
201-
writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
199+
mtk_ddp_write(cmdq_pkt, gmc_value,
200+
comp, DISP_REG_OVL_RDMA_GMC(idx));
201+
mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp,
202+
DISP_REG_OVL_SRC_CON, BIT(idx));
202203
}
203204

204-
static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx)
205+
static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx,
206+
struct cmdq_pkt *cmdq_pkt)
205207
{
206-
unsigned int reg;
207-
208-
reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
209-
reg = reg & ~BIT(idx);
210-
writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
211-
212-
writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
208+
mtk_ddp_write_mask(cmdq_pkt, 0, comp,
209+
DISP_REG_OVL_SRC_CON, BIT(idx));
210+
mtk_ddp_write(cmdq_pkt, 0, comp,
211+
DISP_REG_OVL_RDMA_CTRL(idx));
213212
}
214213

215214
static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
@@ -249,7 +248,8 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
249248
}
250249

251250
static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
252-
struct mtk_plane_state *state)
251+
struct mtk_plane_state *state,
252+
struct cmdq_pkt *cmdq_pkt)
253253
{
254254
struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
255255
struct mtk_plane_pending_state *pending = &state->pending;
@@ -260,11 +260,13 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
260260
unsigned int src_size = (pending->height << 16) | pending->width;
261261
unsigned int con;
262262

263-
if (!pending->enable)
264-
mtk_ovl_layer_off(comp, idx);
263+
if (!pending->enable) {
264+
mtk_ovl_layer_off(comp, idx, cmdq_pkt);
265+
return;
266+
}
265267

266268
con = ovl_fmt_convert(ovl, fmt);
267-
if (idx != 0)
269+
if (state->base.fb->format->has_alpha)
268270
con |= OVL_CON_AEN | OVL_CON_ALPHA;
269271

270272
if (pending->rotation & DRM_MODE_REFLECT_Y) {
@@ -277,14 +279,18 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
277279
addr += pending->pitch - 1;
278280
}
279281

280-
writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx));
281-
writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
282-
writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
283-
writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
284-
writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(ovl, idx));
285-
286-
if (pending->enable)
287-
mtk_ovl_layer_on(comp, idx);
282+
mtk_ddp_write_relaxed(cmdq_pkt, con, comp,
283+
DISP_REG_OVL_CON(idx));
284+
mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp,
285+
DISP_REG_OVL_PITCH(idx));
286+
mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp,
287+
DISP_REG_OVL_SRC_SIZE(idx));
288+
mtk_ddp_write_relaxed(cmdq_pkt, offset, comp,
289+
DISP_REG_OVL_OFFSET(idx));
290+
mtk_ddp_write_relaxed(cmdq_pkt, addr, comp,
291+
DISP_REG_OVL_ADDR(ovl, idx));
292+
293+
mtk_ovl_layer_on(comp, idx, cmdq_pkt);
288294
}
289295

290296
static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
@@ -313,8 +319,6 @@ static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
313319
.disable_vblank = mtk_ovl_disable_vblank,
314320
.supported_rotations = mtk_ovl_supported_rotations,
315321
.layer_nr = mtk_ovl_layer_nr,
316-
.layer_on = mtk_ovl_layer_on,
317-
.layer_off = mtk_ovl_layer_off,
318322
.layer_check = mtk_ovl_layer_check,
319323
.layer_config = mtk_ovl_layer_config,
320324
.bgclr_in_on = mtk_ovl_bgclr_in_on,

‎drivers/gpu/drm/mediatek/mtk_disp_rdma.c

Lines changed: 25 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include <linux/of_device.h>
1010
#include <linux/of_irq.h>
1111
#include <linux/platform_device.h>
12+
#include <linux/soc/mediatek/mtk-cmdq.h>
1213

1314
#include "mtk_drm_crtc.h"
1415
#include "mtk_drm_ddp_comp.h"
@@ -125,14 +126,16 @@ static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
125126

126127
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
127128
unsigned int height, unsigned int vrefresh,
128-
unsigned int bpc)
129+
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
129130
{
130131
unsigned int threshold;
131132
unsigned int reg;
132133
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
133134

134-
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
135-
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
135+
mtk_ddp_write_mask(cmdq_pkt, width, comp,
136+
DISP_REG_RDMA_SIZE_CON_0, 0xfff);
137+
mtk_ddp_write_mask(cmdq_pkt, height, comp,
138+
DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
136139

137140
/*
138141
* Enable FIFO underflow since DSI and DPI can't be blocked.
@@ -144,7 +147,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
144147
reg = RDMA_FIFO_UNDERFLOW_EN |
145148
RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) |
146149
RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
147-
writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
150+
mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON);
148151
}
149152

150153
static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
@@ -190,7 +193,8 @@ static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp)
190193
}
191194

192195
static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
193-
struct mtk_plane_state *state)
196+
struct mtk_plane_state *state,
197+
struct cmdq_pkt *cmdq_pkt)
194198
{
195199
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
196200
struct mtk_plane_pending_state *pending = &state->pending;
@@ -200,24 +204,27 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
200204
unsigned int con;
201205

202206
con = rdma_fmt_convert(rdma, fmt);
203-
writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
207+
mtk_ddp_write_relaxed(cmdq_pkt, con, comp, DISP_RDMA_MEM_CON);
204208

205209
if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
206-
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
207-
RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE);
208-
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
209-
RDMA_MATRIX_INT_MTX_SEL,
210-
RDMA_MATRIX_INT_MTX_BT601_to_RGB);
210+
mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp,
211+
DISP_REG_RDMA_SIZE_CON_0,
212+
RDMA_MATRIX_ENABLE);
213+
mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
214+
comp, DISP_REG_RDMA_SIZE_CON_0,
215+
RDMA_MATRIX_INT_MTX_SEL);
211216
} else {
212-
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
213-
RDMA_MATRIX_ENABLE, 0);
217+
mtk_ddp_write_mask(cmdq_pkt, 0, comp,
218+
DISP_REG_RDMA_SIZE_CON_0,
219+
RDMA_MATRIX_ENABLE);
214220
}
221+
mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, DISP_RDMA_MEM_START_ADDR);
222+
mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, DISP_RDMA_MEM_SRC_PITCH);
223+
mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp,
224+
DISP_RDMA_MEM_GMC_SETTING_0);
225+
mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp,
226+
DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
215227

216-
writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
217-
writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
218-
writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);
219-
rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
220-
RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
221228
}
222229

223230
static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {

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