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Merge tag 'riscv/for-v5.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Paul Walmsley: "Three fixes for RISC-V: - Don't free and reuse memory containing the code that CPUs parked at boot reside in. - Fix rv64 build problems for ubsan and some modules by adding logical and arithmetic shift helpers for 128-bit values. These are from libgcc and are similar to what's present for ARM64. - Fix vDSO builds to clean up their own temporary files" * tag 'riscv/for-v5.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Less inefficient gcc tishift helpers (and export their symbols) riscv: delete temporary files riscv: make sure the cores stay looping in .Lsecondary_park
2 parents 11a8272 + fc585d4 commit 7008ee1

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4 files changed

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4 files changed

+73
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lines changed

arch/riscv/include/asm/asm-prototypes.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,4 +5,8 @@
55
#include <linux/ftrace.h>
66
#include <asm-generic/asm-prototypes.h>
77

8+
long long __lshrti3(long long a, int b);
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long long __ashrti3(long long a, int b);
10+
long long __ashlti3(long long a, int b);
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812
#endif /* _ASM_RISCV_PROTOTYPES_H */

arch/riscv/kernel/head.S

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,9 @@ _start_kernel:
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#ifdef CONFIG_SMP
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li t0, CONFIG_NR_CPUS
83-
bgeu a0, t0, .Lsecondary_park
83+
blt a0, t0, .Lgood_cores
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tail .Lsecondary_park
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.Lgood_cores:
8486
#endif
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/* Pick one hart to run the main boot sequence */
@@ -209,11 +211,6 @@ relocate:
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tail smp_callin
210212
#endif
211213

212-
.align 2
213-
.Lsecondary_park:
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/* We lack SMP support or have too many harts, so park this hart */
215-
wfi
216-
j .Lsecondary_park
217214
END(_start)
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219216
#ifdef CONFIG_RISCV_M_MODE
@@ -295,6 +292,13 @@ ENTRY(reset_regs)
295292
END(reset_regs)
296293
#endif /* CONFIG_RISCV_M_MODE */
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295+
.section ".text", "ax",@progbits
296+
.align 2
297+
.Lsecondary_park:
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/* We lack SMP support or have too many harts, so park this hart */
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wfi
300+
j .Lsecondary_park
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298302
__PAGE_ALIGNED_BSS
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/* Empty zero page */
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.balign PAGE_SIZE

arch/riscv/kernel/vdso/Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,8 @@ quiet_cmd_vdsold = VDSOLD $@
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cmd_vdsold = $(CC) $(KBUILD_CFLAGS) $(call cc-option, -no-pie) -nostdlib -nostartfiles $(SYSCFLAGS_$(@F)) \
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-Wl,-T,$(filter-out FORCE,$^) -o $@.tmp && \
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$(CROSS_COMPILE)objcopy \
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$(patsubst %, -G __vdso_%, $(vdso-syms)) $@.tmp $@
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$(patsubst %, -G __vdso_%, $(vdso-syms)) $@.tmp $@ && \
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rm $@.tmp
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# install commands for the unstripped file
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quiet_cmd_vdso_install = INSTALL $@

arch/riscv/lib/tishift.S

Lines changed: 57 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -4,34 +4,73 @@
44
*/
55

66
#include <linux/linkage.h>
7+
#include <asm-generic/export.h>
78

8-
ENTRY(__lshrti3)
9+
SYM_FUNC_START(__lshrti3)
910
beqz a2, .L1
1011
li a5,64
1112
sub a5,a5,a2
12-
addi sp,sp,-16
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sext.w a4,a5
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blez a5, .L2
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sext.w a2,a2
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sll a4,a1,a4
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srl a0,a0,a2
18-
srl a1,a1,a2
17+
sll a4,a1,a4
18+
srl a2,a1,a2
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or a0,a0,a4
20-
sd a1,8(sp)
21-
sd a0,0(sp)
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ld a0,0(sp)
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ld a1,8(sp)
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addi sp,sp,16
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ret
20+
mv a1,a2
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.L1:
2722
ret
2823
.L2:
29-
negw a4,a4
30-
srl a1,a1,a4
31-
sd a1,0(sp)
32-
sd zero,8(sp)
33-
ld a0,0(sp)
34-
ld a1,8(sp)
35-
addi sp,sp,16
24+
negw a0,a4
25+
li a2,0
26+
srl a0,a1,a0
27+
mv a1,a2
28+
ret
29+
SYM_FUNC_END(__lshrti3)
30+
EXPORT_SYMBOL(__lshrti3)
31+
32+
SYM_FUNC_START(__ashrti3)
33+
beqz a2, .L3
34+
li a5,64
35+
sub a5,a5,a2
36+
sext.w a4,a5
37+
blez a5, .L4
38+
sext.w a2,a2
39+
srl a0,a0,a2
40+
sll a4,a1,a4
41+
sra a2,a1,a2
42+
or a0,a0,a4
43+
mv a1,a2
44+
.L3:
45+
ret
46+
.L4:
47+
negw a0,a4
48+
srai a2,a1,0x3f
49+
sra a0,a1,a0
50+
mv a1,a2
51+
ret
52+
SYM_FUNC_END(__ashrti3)
53+
EXPORT_SYMBOL(__ashrti3)
54+
55+
SYM_FUNC_START(__ashlti3)
56+
beqz a2, .L5
57+
li a5,64
58+
sub a5,a5,a2
59+
sext.w a4,a5
60+
blez a5, .L6
61+
sext.w a2,a2
62+
sll a1,a1,a2
63+
srl a4,a0,a4
64+
sll a2,a0,a2
65+
or a1,a1,a4
66+
mv a0,a2
67+
.L5:
68+
ret
69+
.L6:
70+
negw a1,a4
71+
li a2,0
72+
sll a1,a0,a1
73+
mv a0,a2
3674
ret
37-
ENDPROC(__lshrti3)
75+
SYM_FUNC_END(__ashlti3)
76+
EXPORT_SYMBOL(__ashlti3)

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