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Merge branch 'pci/dt-bindings'
- Add "apb", "sys", "pmc", "msg", "err" for Endpoint descriptions as well as for Root Complexes (Niklas Cassel) - Add "tx_inta", "tx_intb", "tx_intc", "tx_intd" for interrupt signals triggered in response to PCIe Assert_INTx messages (Niklas Cassel) - Refactor rockchip-dw-pcie binding to move generic properties to a new rockchip-dw-pcie-common binding that can be shared by both RC and EP mode (Niklas Cassel) - Fix rockchip-dw-pcie description of INTx signals (Niklas Cassel) - Add rockchip-dw-pcie description of Endpoint controller (Niklas Cassel) - Avoid xilinx-versal-cpm overlapping of bridge registers and 32-bit BAR addresses (Thippeswamy Havalige) - Add qcom Operating Performance Points (OPP) table (Krishna chaitanya chundru) - Add a picture of mediatek,mt7621-pcie topology (Sergio Paracuellos) - Add a generic "ats-supported" property so the OS can discover whether a Root Complex supports ATS (Jean-Philippe Brucker) - Make the qcom,pcie-x1e80100 MHI register region mandatory (Abel Vesa) * pci/dt-bindings: dt-bindings: PCI: qcom: x1e80100: Make the MHI reg region mandatory dt-bindings: PCI: generic: Add ats-supported property dt-bindings: PCI: mediatek,mt7621-pcie: Add PCIe host topology ASCII graph dt-bindings: PCI: qcom: Add OPP table dt-bindings: PCI: xilinx-cpm: Fix overlapping of bridge register and 32-bit BAR addresses dt-bindings: PCI: rockchip: Add DesignWare based PCIe Endpoint controller dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy IRQ dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy IRQs dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name
2 parents 65d8f68 + 30e7c6c commit 7095d21

9 files changed

+276
-95
lines changed

‎Documentation/devicetree/bindings/pci/host-generic-pci.yaml

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iommu-map-mask: true
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msi-parent: true
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ats-supported:
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description:
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Indicates that a PCIe host controller supports ATS, and can handle Memory
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Requests with Address Type (AT).
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type: boolean
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml

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MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
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with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
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MT7621 PCIe HOST Topology
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.-------.
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| |
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| CPU |
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| |
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'-------'
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|
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|
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|
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v
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.------------------.
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.-----------| HOST/PCI Bridge |------------.
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| '------------------' | Type1
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BUS0 | | | Access
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v v v On Bus0
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.-------------. .-------------. .-------------.
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| VIRTUAL P2P | | VIRTUAL P2P | | VIRTUAL P2P |
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| BUS0 | | BUS0 | | BUS0 |
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| DEV0 | | DEV1 | | DEV2 |
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'-------------' '-------------' '-------------'
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Type0 | Type0 | Type0 |
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Access BUS1 | Access BUS2| Access BUS3|
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On Bus1 v On Bus2 v On Bus3 v
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.----------. .----------. .----------.
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| Device 0 | | Device 0 | | Device 0 |
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| Func 0 | | Func 0 | | Func 0 |
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'----------' '----------' '----------'
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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‎Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml

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- const: msi6
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- const: msi7
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operating-points-v2: true
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opp-table:
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type: object
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resets:
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maxItems: 1
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‎Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml

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const: qcom,pcie-x1e80100
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reg:
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minItems: 5
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minItems: 6
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maxItems: 6
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reg-names:
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minItems: 5
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers

‎Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
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maintainers:
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- Shawn Lin <[email protected]>
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- Simon Xue <[email protected]>
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- Heiko Stuebner <[email protected]>
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description: |+
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Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
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SoCs.
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properties:
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clocks:
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minItems: 5
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items:
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- description: AHB clock for PCIe master
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- description: AHB clock for PCIe slave
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- description: AHB clock for PCIe dbi
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- description: APB clock for PCIe
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- description: Auxiliary clock for PCIe
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- description: PIPE clock
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- description: Reference clock for PCIe
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clock-names:
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minItems: 5
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items:
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- const: aclk_mst
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- const: aclk_slv
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- const: aclk_dbi
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- const: pclk
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- const: aux
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- const: pipe
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- const: ref
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interrupts:
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minItems: 5
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items:
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- description:
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Combined system interrupt, which is used to signal the following
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interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
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hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
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edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
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- description:
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Combined PM interrupt, which is used to signal the following
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interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
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linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
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linkst_out_l0s, pm_dstate_update
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- description:
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Combined message interrupt, which is used to signal the following
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interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
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pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
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- description:
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Combined legacy interrupt, which is used to signal the following
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interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc,
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tx_intd
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- description:
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Combined error interrupt, which is used to signal the following
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interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
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tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
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nf_err_rx, f_err_rx, radm_qoverflow
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- description:
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eDMA write channel 0 interrupt
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- description:
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eDMA write channel 1 interrupt
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- description:
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eDMA read channel 0 interrupt
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- description:
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eDMA read channel 1 interrupt
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interrupt-names:
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minItems: 5
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items:
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- const: sys
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- const: pmc
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- const: msg
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- const: legacy
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- const: err
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- const: dma0
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- const: dma1
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- const: dma2
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- const: dma3
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num-lanes: true
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phys:
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maxItems: 1
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phy-names:
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const: pcie-phy
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power-domains:
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maxItems: 1
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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oneOf:
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- const: pipe
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- items:
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- const: pwr
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- const: pipe
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- num-lanes
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- phys
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- phy-names
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- power-domains
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- resets
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- reset-names
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additionalProperties: true
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...

‎Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
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maintainers:
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- Niklas Cassel <[email protected]>
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description: |+
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RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
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PCIe IP and thus inherits all the common properties defined in
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snps,dw-pcie-ep.yaml.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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- $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
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properties:
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compatible:
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enum:
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- rockchip,rk3568-pcie-ep
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- rockchip,rk3588-pcie-ep
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reg:
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items:
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- description: Data Bus Interface (DBI) registers
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- description: Data Bus Interface (DBI) shadow registers
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- description: Rockchip designed configuration registers
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- description: Memory region used to map remote RC address space
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- description: Internal Address Translation Unit (iATU) registers
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: apb
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- const: addr_space
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- const: atu
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required:
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- interrupts
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- interrupt-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/rk3588-power.h>
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie3x4_ep: pcie-ep@fe150000 {
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compatible = "rockchip,rk3588-pcie-ep";
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reg = <0xa 0x40000000 0x0 0x00100000>,
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<0xa 0x40100000 0x0 0x00100000>,
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<0x0 0xfe150000 0x0 0x00010000>,
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<0x9 0x00000000 0x0 0x40000000>,
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<0xa 0x40300000 0x0 0x00100000>;
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reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
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clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
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<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
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<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux", "pipe";
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interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err",
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"dma0", "dma1", "dma2", "dma3";
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max-link-speed = <3>;
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num-lanes = <4>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PCIE>;
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resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
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reset-names = "pwr", "pipe";
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};
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};
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...

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