@@ -43,46 +43,19 @@ dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)
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return NULL ;
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}
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- static unsigned int dw_pcie_ep_get_dbi_offset (struct dw_pcie_ep * ep , u8 func_no )
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- {
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- unsigned int dbi_offset = 0 ;
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-
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- if (ep -> ops -> get_dbi_offset )
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- dbi_offset = ep -> ops -> get_dbi_offset (ep , func_no );
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-
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- return dbi_offset ;
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- }
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-
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- static unsigned int dw_pcie_ep_get_dbi2_offset (struct dw_pcie_ep * ep , u8 func_no )
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- {
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- unsigned int dbi2_offset = 0 ;
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-
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- if (ep -> ops -> get_dbi2_offset )
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- dbi2_offset = ep -> ops -> get_dbi2_offset (ep , func_no );
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- else if (ep -> ops -> get_dbi_offset ) /* for backward compatibility */
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- dbi2_offset = ep -> ops -> get_dbi_offset (ep , func_no );
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-
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- return dbi2_offset ;
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- }
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-
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static void __dw_pcie_ep_reset_bar (struct dw_pcie * pci , u8 func_no ,
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enum pci_barno bar , int flags )
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{
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- unsigned int dbi_offset , dbi2_offset ;
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struct dw_pcie_ep * ep = & pci -> ep ;
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- u32 reg , reg_dbi2 ;
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-
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- dbi_offset = dw_pcie_ep_get_dbi_offset (ep , func_no );
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- dbi2_offset = dw_pcie_ep_get_dbi2_offset (ep , func_no );
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+ u32 reg ;
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- reg = dbi_offset + PCI_BASE_ADDRESS_0 + (4 * bar );
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- reg_dbi2 = dbi2_offset + PCI_BASE_ADDRESS_0 + (4 * bar );
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+ reg = PCI_BASE_ADDRESS_0 + (4 * bar );
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dw_pcie_dbi_ro_wr_en (pci );
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- dw_pcie_writel_dbi2 ( pci , reg_dbi2 , 0x0 );
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- dw_pcie_writel_dbi ( pci , reg , 0x0 );
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+ dw_pcie_ep_writel_dbi2 ( ep , func_no , reg , 0x0 );
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+ dw_pcie_ep_writel_dbi ( ep , func_no , reg , 0x0 );
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if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64 ) {
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- dw_pcie_writel_dbi2 ( pci , reg_dbi2 + 4 , 0x0 );
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- dw_pcie_writel_dbi ( pci , reg + 4 , 0x0 );
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+ dw_pcie_ep_writel_dbi2 ( ep , func_no , reg + 4 , 0x0 );
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+ dw_pcie_ep_writel_dbi ( ep , func_no , reg + 4 , 0x0 );
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}
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dw_pcie_dbi_ro_wr_dis (pci );
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}
@@ -99,19 +72,15 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
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EXPORT_SYMBOL_GPL (dw_pcie_ep_reset_bar );
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static u8 __dw_pcie_ep_find_next_cap (struct dw_pcie_ep * ep , u8 func_no ,
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- u8 cap_ptr , u8 cap )
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+ u8 cap_ptr , u8 cap )
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{
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- struct dw_pcie * pci = to_dw_pcie_from_ep (ep );
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- unsigned int dbi_offset = 0 ;
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u8 cap_id , next_cap_ptr ;
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u16 reg ;
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if (!cap_ptr )
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return 0 ;
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- dbi_offset = dw_pcie_ep_get_dbi_offset (ep , func_no );
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-
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- reg = dw_pcie_readw_dbi (pci , dbi_offset + cap_ptr );
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+ reg = dw_pcie_ep_readw_dbi (ep , func_no , cap_ptr );
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cap_id = (reg & 0x00ff );
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if (cap_id > PCI_CAP_ID_MAX )
@@ -126,14 +95,10 @@ static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, u8 func_no,
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static u8 dw_pcie_ep_find_capability (struct dw_pcie_ep * ep , u8 func_no , u8 cap )
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{
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- struct dw_pcie * pci = to_dw_pcie_from_ep (ep );
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- unsigned int dbi_offset = 0 ;
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u8 next_cap_ptr ;
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u16 reg ;
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- dbi_offset = dw_pcie_ep_get_dbi_offset (ep , func_no );
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-
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- reg = dw_pcie_readw_dbi (pci , dbi_offset + PCI_CAPABILITY_LIST );
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+ reg = dw_pcie_ep_readw_dbi (ep , func_no , PCI_CAPABILITY_LIST );
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next_cap_ptr = (reg & 0x00ff );
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return __dw_pcie_ep_find_next_cap (ep , func_no , next_cap_ptr , cap );
@@ -144,24 +109,21 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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{
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struct dw_pcie_ep * ep = epc_get_drvdata (epc );
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struct dw_pcie * pci = to_dw_pcie_from_ep (ep );
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- unsigned int dbi_offset = 0 ;
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-
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- dbi_offset = dw_pcie_ep_get_dbi_offset (ep , func_no );
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dw_pcie_dbi_ro_wr_en (pci );
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- dw_pcie_writew_dbi ( pci , dbi_offset + PCI_VENDOR_ID , hdr -> vendorid );
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- dw_pcie_writew_dbi ( pci , dbi_offset + PCI_DEVICE_ID , hdr -> deviceid );
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- dw_pcie_writeb_dbi ( pci , dbi_offset + PCI_REVISION_ID , hdr -> revid );
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- dw_pcie_writeb_dbi ( pci , dbi_offset + PCI_CLASS_PROG , hdr -> progif_code );
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- dw_pcie_writew_dbi ( pci , dbi_offset + PCI_CLASS_DEVICE ,
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- hdr -> subclass_code | hdr -> baseclass_code << 8 );
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- dw_pcie_writeb_dbi ( pci , dbi_offset + PCI_CACHE_LINE_SIZE ,
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- hdr -> cache_line_size );
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- dw_pcie_writew_dbi ( pci , dbi_offset + PCI_SUBSYSTEM_VENDOR_ID ,
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- hdr -> subsys_vendor_id );
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- dw_pcie_writew_dbi ( pci , dbi_offset + PCI_SUBSYSTEM_ID , hdr -> subsys_id );
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- dw_pcie_writeb_dbi ( pci , dbi_offset + PCI_INTERRUPT_PIN ,
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- hdr -> interrupt_pin );
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+ dw_pcie_ep_writew_dbi ( ep , func_no , PCI_VENDOR_ID , hdr -> vendorid );
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+ dw_pcie_ep_writew_dbi ( ep , func_no , PCI_DEVICE_ID , hdr -> deviceid );
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+ dw_pcie_ep_writeb_dbi ( ep , func_no , PCI_REVISION_ID , hdr -> revid );
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+ dw_pcie_ep_writeb_dbi ( ep , func_no , PCI_CLASS_PROG , hdr -> progif_code );
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+ dw_pcie_ep_writew_dbi ( ep , func_no , PCI_CLASS_DEVICE ,
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+ hdr -> subclass_code | hdr -> baseclass_code << 8 );
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+ dw_pcie_ep_writeb_dbi ( ep , func_no , PCI_CACHE_LINE_SIZE ,
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+ hdr -> cache_line_size );
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+ dw_pcie_ep_writew_dbi ( ep , func_no , PCI_SUBSYSTEM_VENDOR_ID ,
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+ hdr -> subsys_vendor_id );
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+ dw_pcie_ep_writew_dbi ( ep , func_no , PCI_SUBSYSTEM_ID , hdr -> subsys_id );
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+ dw_pcie_ep_writeb_dbi ( ep , func_no , PCI_INTERRUPT_PIN ,
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+ hdr -> interrupt_pin );
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dw_pcie_dbi_ro_wr_dis (pci );
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return 0 ;
@@ -243,18 +205,13 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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{
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struct dw_pcie_ep * ep = epc_get_drvdata (epc );
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struct dw_pcie * pci = to_dw_pcie_from_ep (ep );
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- unsigned int dbi_offset , dbi2_offset ;
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enum pci_barno bar = epf_bar -> barno ;
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size_t size = epf_bar -> size ;
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int flags = epf_bar -> flags ;
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- u32 reg , reg_dbi2 ;
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int ret , type ;
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+ u32 reg ;
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- dbi_offset = dw_pcie_ep_get_dbi_offset (ep , func_no );
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- dbi2_offset = dw_pcie_ep_get_dbi2_offset (ep , func_no );
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-
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- reg = PCI_BASE_ADDRESS_0 + (4 * bar ) + dbi_offset ;
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- reg_dbi2 = PCI_BASE_ADDRESS_0 + (4 * bar ) + dbi2_offset ;
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+ reg = PCI_BASE_ADDRESS_0 + (4 * bar );
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if (!(flags & PCI_BASE_ADDRESS_SPACE ))
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type = PCIE_ATU_TYPE_MEM ;
@@ -270,12 +227,12 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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dw_pcie_dbi_ro_wr_en (pci );
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- dw_pcie_writel_dbi2 ( pci , reg_dbi2 , lower_32_bits (size - 1 ));
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- dw_pcie_writel_dbi ( pci , reg , flags );
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+ dw_pcie_ep_writel_dbi2 ( ep , func_no , reg , lower_32_bits (size - 1 ));
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+ dw_pcie_ep_writel_dbi ( ep , func_no , reg , flags );
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if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64 ) {
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- dw_pcie_writel_dbi2 ( pci , reg_dbi2 + 4 , upper_32_bits (size - 1 ));
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- dw_pcie_writel_dbi ( pci , reg + 4 , 0 );
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+ dw_pcie_ep_writel_dbi2 ( ep , func_no , reg + 4 , upper_32_bits (size - 1 ));
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+ dw_pcie_ep_writel_dbi ( ep , func_no , reg + 4 , 0 );
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}
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ep -> epf_bar [bar ] = epf_bar ;
@@ -335,19 +292,15 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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static int dw_pcie_ep_get_msi (struct pci_epc * epc , u8 func_no , u8 vfunc_no )
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{
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struct dw_pcie_ep * ep = epc_get_drvdata (epc );
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- struct dw_pcie * pci = to_dw_pcie_from_ep (ep );
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- u32 val , reg ;
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- unsigned int dbi_offset = 0 ;
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struct dw_pcie_ep_func * ep_func ;
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+ u32 val , reg ;
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ep_func = dw_pcie_ep_get_func_from_ep (ep , func_no );
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if (!ep_func || !ep_func -> msi_cap )
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return - EINVAL ;
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- dbi_offset = dw_pcie_ep_get_dbi_offset (ep , func_no );
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-
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- reg = ep_func -> msi_cap + dbi_offset + PCI_MSI_FLAGS ;
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- val = dw_pcie_readw_dbi (pci , reg );
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+ reg = ep_func -> msi_cap + PCI_MSI_FLAGS ;
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+ val = dw_pcie_ep_readw_dbi (ep , func_no , reg );
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if (!(val & PCI_MSI_FLAGS_ENABLE ))
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return - EINVAL ;
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@@ -361,22 +314,19 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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{
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struct dw_pcie_ep * ep = epc_get_drvdata (epc );
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struct dw_pcie * pci = to_dw_pcie_from_ep (ep );
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- u32 val , reg ;
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- unsigned int dbi_offset = 0 ;
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struct dw_pcie_ep_func * ep_func ;
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+ u32 val , reg ;
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ep_func = dw_pcie_ep_get_func_from_ep (ep , func_no );
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if (!ep_func || !ep_func -> msi_cap )
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return - EINVAL ;
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- dbi_offset = dw_pcie_ep_get_dbi_offset (ep , func_no );
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-
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- reg = ep_func -> msi_cap + dbi_offset + PCI_MSI_FLAGS ;
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- val = dw_pcie_readw_dbi (pci , reg );
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+ reg = ep_func -> msi_cap + PCI_MSI_FLAGS ;
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+ val = dw_pcie_ep_readw_dbi (ep , func_no , reg );
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val &= ~PCI_MSI_FLAGS_QMASK ;
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val |= FIELD_PREP (PCI_MSI_FLAGS_QMASK , interrupts );
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dw_pcie_dbi_ro_wr_en (pci );
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- dw_pcie_writew_dbi ( pci , reg , val );
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+ dw_pcie_ep_writew_dbi ( ep , func_no , reg , val );
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dw_pcie_dbi_ro_wr_dis (pci );
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return 0 ;
@@ -385,19 +335,15 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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static int dw_pcie_ep_get_msix (struct pci_epc * epc , u8 func_no , u8 vfunc_no )
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{
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struct dw_pcie_ep * ep = epc_get_drvdata (epc );
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- struct dw_pcie * pci = to_dw_pcie_from_ep (ep );
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- u32 val , reg ;
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- unsigned int dbi_offset = 0 ;
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struct dw_pcie_ep_func * ep_func ;
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+ u32 val , reg ;
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ep_func = dw_pcie_ep_get_func_from_ep (ep , func_no );
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if (!ep_func || !ep_func -> msix_cap )
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return - EINVAL ;
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- dbi_offset = dw_pcie_ep_get_dbi_offset (ep , func_no );
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-
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- reg = ep_func -> msix_cap + dbi_offset + PCI_MSIX_FLAGS ;
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- val = dw_pcie_readw_dbi (pci , reg );
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+ reg = ep_func -> msix_cap + PCI_MSIX_FLAGS ;
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+ val = dw_pcie_ep_readw_dbi (ep , func_no , reg );
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if (!(val & PCI_MSIX_FLAGS_ENABLE ))
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return - EINVAL ;
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@@ -411,31 +357,28 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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{
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struct dw_pcie_ep * ep = epc_get_drvdata (epc );
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struct dw_pcie * pci = to_dw_pcie_from_ep (ep );
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- u32 val , reg ;
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- unsigned int dbi_offset = 0 ;
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struct dw_pcie_ep_func * ep_func ;
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+ u32 val , reg ;
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ep_func = dw_pcie_ep_get_func_from_ep (ep , func_no );
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if (!ep_func || !ep_func -> msix_cap )
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return - EINVAL ;
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dw_pcie_dbi_ro_wr_en (pci );
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- dbi_offset = dw_pcie_ep_get_dbi_offset (ep , func_no );
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-
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- reg = ep_func -> msix_cap + dbi_offset + PCI_MSIX_FLAGS ;
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- val = dw_pcie_readw_dbi (pci , reg );
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+ reg = ep_func -> msix_cap + PCI_MSIX_FLAGS ;
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+ val = dw_pcie_ep_readw_dbi (ep , func_no , reg );
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val &= ~PCI_MSIX_FLAGS_QSIZE ;
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val |= interrupts ;
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dw_pcie_writew_dbi (pci , reg , val );
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- reg = ep_func -> msix_cap + dbi_offset + PCI_MSIX_TABLE ;
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+ reg = ep_func -> msix_cap + PCI_MSIX_TABLE ;
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val = offset | bir ;
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- dw_pcie_writel_dbi ( pci , reg , val );
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+ dw_pcie_ep_writel_dbi ( ep , func_no , reg , val );
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- reg = ep_func -> msix_cap + dbi_offset + PCI_MSIX_PBA ;
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+ reg = ep_func -> msix_cap + PCI_MSIX_PBA ;
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val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE )) | bir ;
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- dw_pcie_writel_dbi ( pci , reg , val );
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+ dw_pcie_ep_writel_dbi ( ep , func_no , reg , val );
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dw_pcie_dbi_ro_wr_dis (pci );
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@@ -510,38 +453,34 @@ EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_legacy_irq);
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int dw_pcie_ep_raise_msi_irq (struct dw_pcie_ep * ep , u8 func_no ,
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u8 interrupt_num )
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{
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- struct dw_pcie * pci = to_dw_pcie_from_ep ( ep ) ;
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+ u32 msg_addr_lower , msg_addr_upper , reg ;
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struct dw_pcie_ep_func * ep_func ;
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struct pci_epc * epc = ep -> epc ;
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unsigned int aligned_offset ;
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- unsigned int dbi_offset = 0 ;
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u16 msg_ctrl , msg_data ;
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- u32 msg_addr_lower , msg_addr_upper , reg ;
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- u64 msg_addr ;
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bool has_upper ;
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+ u64 msg_addr ;
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int ret ;
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ep_func = dw_pcie_ep_get_func_from_ep (ep , func_no );
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if (!ep_func || !ep_func -> msi_cap )
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return - EINVAL ;
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- dbi_offset = dw_pcie_ep_get_dbi_offset (ep , func_no );
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-
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/* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
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- reg = ep_func -> msi_cap + dbi_offset + PCI_MSI_FLAGS ;
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- msg_ctrl = dw_pcie_readw_dbi ( pci , reg );
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+ reg = ep_func -> msi_cap + PCI_MSI_FLAGS ;
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+ msg_ctrl = dw_pcie_ep_readw_dbi ( ep , func_no , reg );
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has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT );
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- reg = ep_func -> msi_cap + dbi_offset + PCI_MSI_ADDRESS_LO ;
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- msg_addr_lower = dw_pcie_readl_dbi ( pci , reg );
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+ reg = ep_func -> msi_cap + PCI_MSI_ADDRESS_LO ;
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+ msg_addr_lower = dw_pcie_ep_readl_dbi ( ep , func_no , reg );
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if (has_upper ) {
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- reg = ep_func -> msi_cap + dbi_offset + PCI_MSI_ADDRESS_HI ;
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- msg_addr_upper = dw_pcie_readl_dbi ( pci , reg );
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- reg = ep_func -> msi_cap + dbi_offset + PCI_MSI_DATA_64 ;
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- msg_data = dw_pcie_readw_dbi ( pci , reg );
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+ reg = ep_func -> msi_cap + PCI_MSI_ADDRESS_HI ;
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+ msg_addr_upper = dw_pcie_ep_readl_dbi ( ep , func_no , reg );
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+ reg = ep_func -> msi_cap + PCI_MSI_DATA_64 ;
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+ msg_data = dw_pcie_ep_readw_dbi ( ep , func_no , reg );
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} else {
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msg_addr_upper = 0 ;
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- reg = ep_func -> msi_cap + dbi_offset + PCI_MSI_DATA_32 ;
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- msg_data = dw_pcie_readw_dbi ( pci , reg );
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+ reg = ep_func -> msi_cap + PCI_MSI_DATA_32 ;
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+ msg_data = dw_pcie_ep_readw_dbi ( ep , func_no , reg );
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}
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aligned_offset = msg_addr_lower & (epc -> mem -> window .page_size - 1 );
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msg_addr = ((u64 )msg_addr_upper ) << 32 |
@@ -582,10 +521,9 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
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u16 interrupt_num )
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{
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struct dw_pcie * pci = to_dw_pcie_from_ep (ep );
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- struct dw_pcie_ep_func * ep_func ;
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struct pci_epf_msix_tbl * msix_tbl ;
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+ struct dw_pcie_ep_func * ep_func ;
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struct pci_epc * epc = ep -> epc ;
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- unsigned int dbi_offset = 0 ;
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u32 reg , msg_data , vec_ctrl ;
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unsigned int aligned_offset ;
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u32 tbl_offset ;
@@ -597,10 +535,8 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
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if (!ep_func || !ep_func -> msix_cap )
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return - EINVAL ;
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- dbi_offset = dw_pcie_ep_get_dbi_offset (ep , func_no );
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-
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- reg = ep_func -> msix_cap + dbi_offset + PCI_MSIX_TABLE ;
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- tbl_offset = dw_pcie_readl_dbi (pci , reg );
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+ reg = ep_func -> msix_cap + PCI_MSIX_TABLE ;
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+ tbl_offset = dw_pcie_ep_readl_dbi (ep , func_no , reg );
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bir = FIELD_GET (PCI_MSIX_TABLE_BIR , tbl_offset );
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tbl_offset &= PCI_MSIX_TABLE_OFFSET ;
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