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LoongArch: Add misc common routines
Add some misc common routines for LoongArch, including: asm-offsets routines, futex functions, i/o memory access functions, frame-buffer functions, procfs information display, etc. Reviewed-by: WANG Xuerui <[email protected]> Reviewed-by: Jiaxun Yang <[email protected]> Signed-off-by: Huacai Chen <[email protected]>
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‎arch/loongarch/include/asm/asm-offsets.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <generated/asm-offsets.h>

‎arch/loongarch/include/asm/fb.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_FB_H_
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#define _ASM_FB_H_
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#include <linux/fb.h>
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#include <linux/fs.h>
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#include <asm/page.h>
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static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
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unsigned long off)
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{
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vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
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}
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static inline int fb_is_primary_device(struct fb_info *info)
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{
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return 0;
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}
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#endif /* _ASM_FB_H_ */

‎arch/loongarch/include/asm/futex.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_FUTEX_H
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#define _ASM_FUTEX_H
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/barrier.h>
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#include <asm/compiler.h>
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#include <asm/errno.h>
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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{ \
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__asm__ __volatile__( \
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"1: ll.w %1, %4 # __futex_atomic_op\n" \
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" " insn " \n" \
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"2: sc.w $t0, %2 \n" \
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" beq $t0, $zero, 1b \n" \
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"3: \n" \
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" .section .fixup,\"ax\" \n" \
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"4: li.w %0, %6 \n" \
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" b 3b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" "__UA_ADDR "\t1b, 4b \n" \
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" "__UA_ADDR "\t2b, 4b \n" \
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" .previous \n" \
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: "=r" (ret), "=&r" (oldval), \
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"=ZC" (*uaddr) \
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: "0" (0), "ZC" (*uaddr), "Jr" (oparg), \
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"i" (-EFAULT) \
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: "memory", "t0"); \
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}
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static inline int
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arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
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{
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int oldval = 0, ret = 0;
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("move $t0, %z5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("add.w $t0, %1, %z5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("or $t0, %1, %z5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("and $t0, %1, %z5", ret, oldval, uaddr, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("xor $t0, %1, %z5", ret, oldval, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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if (!ret)
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*oval = oldval;
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, u32 newval)
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{
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int ret = 0;
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u32 val = 0;
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if (!access_ok(uaddr, sizeof(u32)))
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return -EFAULT;
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__asm__ __volatile__(
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"# futex_atomic_cmpxchg_inatomic \n"
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"1: ll.w %1, %3 \n"
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" bne %1, %z4, 3f \n"
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" or $t0, %z5, $zero \n"
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"2: sc.w $t0, %2 \n"
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" beq $zero, $t0, 1b \n"
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"3: \n"
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" .section .fixup,\"ax\" \n"
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"4: li.d %0, %6 \n"
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" b 3b \n"
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" .previous \n"
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" .section __ex_table,\"a\" \n"
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" "__UA_ADDR "\t1b, 4b \n"
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" "__UA_ADDR "\t2b, 4b \n"
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" .previous \n"
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: "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
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: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
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"i" (-EFAULT)
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: "memory", "t0");
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*uval = val;
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return ret;
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}
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#endif /* _ASM_FUTEX_H */

‎arch/loongarch/include/asm/io.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_IO_H
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#define _ASM_IO_H
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#define ARCH_HAS_IOREMAP_WC
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/bug.h>
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#include <asm/byteorder.h>
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#include <asm/cpu.h>
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#include <asm/page.h>
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#include <asm/pgtable-bits.h>
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#include <asm/string.h>
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/*
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* On LoongArch, I/O ports mappring is following:
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*
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* | .... |
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* |-----------------------|
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* | pci io ports(64K~32M) |
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* |-----------------------|
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* | isa io ports(0 ~16K) |
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* PCI_IOBASE ->|-----------------------|
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* | .... |
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*/
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#define PCI_IOBASE ((void __iomem *)(vm_map_base + (2 * PAGE_SIZE)))
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#define PCI_IOSIZE SZ_32M
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#define ISA_IOSIZE SZ_16K
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#define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
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/*
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* Change "struct page" to physical address.
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*/
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#define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
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extern void __init __iomem *early_ioremap(u64 phys_addr, unsigned long size);
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extern void __init early_iounmap(void __iomem *addr, unsigned long size);
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#define early_memremap early_ioremap
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#define early_memunmap early_iounmap
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static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
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unsigned long prot_val)
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{
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if (prot_val == _CACHE_CC)
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return (void __iomem *)(unsigned long)(CACHE_BASE + offset);
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else
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return (void __iomem *)(unsigned long)(UNCACHE_BASE + offset);
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}
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/*
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* ioremap - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*/
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#define ioremap(offset, size) \
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ioremap_prot((offset), (size), _CACHE_SUC)
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/*
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* ioremap_wc - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap_wc performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked uncachable
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* but accelerated by means of write-combining feature. It is specifically
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* useful for PCIe prefetchable windows, which may vastly improve a
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* communications performance. If it was determined on boot stage, what
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* CPU CCA doesn't support WUC, the method shall fall-back to the
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* _CACHE_SUC option (see cpu_probe() method).
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*/
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#define ioremap_wc(offset, size) \
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ioremap_prot((offset), (size), _CACHE_WUC)
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/*
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* ioremap_cache - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap_cache performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked cachable by
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* the CPU. Also enables full write-combining. Useful for some
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* memory-like regions on I/O busses.
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*/
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#define ioremap_cache(offset, size) \
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ioremap_prot((offset), (size), _CACHE_CC)
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static inline void iounmap(const volatile void __iomem *addr)
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{
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}
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#define mmiowb() asm volatile ("dbar 0" ::: "memory")
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/*
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* String version of I/O memory access operations.
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*/
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extern void __memset_io(volatile void __iomem *dst, int c, size_t count);
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extern void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count);
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extern void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count);
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#define memset_io(c, v, l) __memset_io((c), (v), (l))
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#define memcpy_fromio(a, c, l) __memcpy_fromio((a), (c), (l))
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#define memcpy_toio(c, a, l) __memcpy_toio((c), (a), (l))
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#include <asm-generic/io.h>
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#endif /* _ASM_IO_H */

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