@@ -27,14 +27,13 @@ static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw,
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NULL , 0 , data -> div .width );
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}
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- static long meson_clk_cpu_dyndiv_round_rate (struct clk_hw * hw ,
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- unsigned long rate ,
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- unsigned long * prate )
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+ static int meson_clk_cpu_dyndiv_determine_rate (struct clk_hw * hw ,
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+ struct clk_rate_request * req )
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{
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struct clk_regmap * clk = to_clk_regmap (hw );
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struct meson_clk_cpu_dyndiv_data * data = meson_clk_cpu_dyndiv_data (clk );
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- return divider_round_rate (hw , rate , prate , NULL , data -> div .width , 0 );
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+ return divider_determine_rate (hw , req , NULL , data -> div .width , 0 );
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}
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static int meson_clk_cpu_dyndiv_set_rate (struct clk_hw * hw , unsigned long rate ,
@@ -63,7 +62,7 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
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const struct clk_ops meson_clk_cpu_dyndiv_ops = {
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.recalc_rate = meson_clk_cpu_dyndiv_recalc_rate ,
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- .round_rate = meson_clk_cpu_dyndiv_round_rate ,
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+ .determine_rate = meson_clk_cpu_dyndiv_determine_rate ,
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.set_rate = meson_clk_cpu_dyndiv_set_rate ,
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};
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EXPORT_SYMBOL_GPL (meson_clk_cpu_dyndiv_ops );
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