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Merge tag 'qcom-arm64-for-6.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
More Qualcomm ARM64 Devicetree updated for v6.4 Devicetree for the QCM2210/QCM2290 is introduced. Support for the RB1 board is introduced on QRB2210, RB2 on QRB4210, the AL02 board on IPQ9574, the MI01.6 board is introduced on IPQ5332 and initial support for Xiaomi Mi A3 is introduced on SM6125. Support for the output-enable/disable flag is introduced in the pinctrl-msm driver, and the non-standard "input-enable" is dropped from a range of platforms. A wide range of smaller fixes are introduced, based on Devicetree validation. MSM8953 gains LPASS, MPSS and Wireless subsystem support. The iommus property is removed from PCIe nodes in all platforms, as the only the child devices should be associated with iommu groups, through the existing iommu-map property. A few QUP instances are introduced on the IPQ5332 platform, and support for the MI01.6 board is introduced. The reserved-memory map on Huawei Nexus 6P is updated with the addition of splash screen framebuffer memory and adjustment to the reserved memory region overlapping the smem region. Regulators are introduces for the SA8775P Ride platform. A regulator is marked always-on, for correctness, on Trogdor. Pinconf fixes are introduced to both sc7180 and sc7280 devices. A dedicated reviewers list is added for boards relevant to the Chromebook engineers. A set of pinconf fixes are introduced for sc8280xp, labels are introduced for Soundwire nodes. The sensor core remoteproc and FastRPC thereon, is introduce in SDM845 and enabled for OnePlus 6/6T and Shift Shift6mq. RMTFS, remoteprocs, ath10k and ramoops is introduced for the Lenovo Tab P11. UFS support is introduced on SM6125. SM8150 no longer defines the GPU to be in headless mode by default, GPU speedbins are introduced. GPU speedbins are introduced for SM8250 as well, as is support for display on Xiaomi Mi Pad 5 Pro, with two different panels supported. Soundwire controllers, ADSP audio codec macros and the Inline Crypto Engine support is added to the SM8550 platform. * tag 'qcom-arm64-for-6.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (85 commits) arm64: dts: qcom: Add base qrb4210-rb2 board dts arm64: dts: qcom: sm8550: add Soundwire controllers arm64: dts: qcom: sm8250: Add GPU speedbin support arm64: dts: qcom: sm8150: Add GPU speedbin support arm64: dts: qcom: sm8150: Don't start Adreno in headless mode arm64: dts: qcom: ipq5332: add support for the RDP468 variant arm64: dts: qcom: sdm630: move DSI opp-table out of DSI node arm64: dts: qcom: sm6115p-j606f: Enable ATH10K WiFi arm64: dts: qcom: sm6115p-j606f: Enable remoteprocs arm64: dts: qcom: sm6115: Add RMTFS arm64: dts: qcom: sm6115-j606f: Add ramoops node arm64: dts: qcom: msm8916-thwc-ufi001c: add function to pin config arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node arm64: dts: MSM8953: Add lpass nodes arm64: dts: MSM8953: Add mpss nodes arm64: dts: MSM8953: Add wcnss nodes arm64: dts: qcom: sm8350: remove superfluous "input-enable" arm64: dts: qcom: sm8150: remove superfluous "input-enable" arm64: dts: qcom: apq8016: remove superfluous "input-enable" arm64: dts: qcom: sc8280xp-lenovo-thinkpad: correct pin drive-strength ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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‎Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml

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@@ -0,0 +1,61 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm Global Clock & Reset Controller on IPQ9574
8+
9+
maintainers:
10+
- Anusha Rao <[email protected]>
11+
12+
description: |
13+
Qualcomm global clock control module provides the clocks, resets and power
14+
domains on IPQ9574
15+
16+
See also::
17+
include/dt-bindings/clock/qcom,ipq9574-gcc.h
18+
include/dt-bindings/reset/qcom,ipq9574-gcc.h
19+
20+
properties:
21+
compatible:
22+
const: qcom,ipq9574-gcc
23+
24+
clocks:
25+
items:
26+
- description: Board XO source
27+
- description: Sleep clock source
28+
- description: Bias PLL ubi clock source
29+
- description: PCIE30 PHY0 pipe clock source
30+
- description: PCIE30 PHY1 pipe clock source
31+
- description: PCIE30 PHY2 pipe clock source
32+
- description: PCIE30 PHY3 pipe clock source
33+
- description: USB3 PHY pipe clock source
34+
35+
required:
36+
- compatible
37+
- clocks
38+
39+
allOf:
40+
- $ref: qcom,gcc.yaml#
41+
42+
unevaluatedProperties: false
43+
44+
examples:
45+
- |
46+
clock-controller@1800000 {
47+
compatible = "qcom,ipq9574-gcc";
48+
reg = <0x01800000 0x80000>;
49+
clocks = <&xo_board_clk>,
50+
<&sleep_clk>,
51+
<&bias_pll_ubi_nc_clk>,
52+
<&pcie30_phy0_pipe_clk>,
53+
<&pcie30_phy1_pipe_clk>,
54+
<&pcie30_phy2_pipe_clk>,
55+
<&pcie30_phy3_pipe_clk>,
56+
<&usb3phy_0_cc_pipe_clk>;
57+
#clock-cells = <1>;
58+
#reset-cells = <1>;
59+
#power-domain-cells = <1>;
60+
};
61+
...

‎Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml

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Original file line numberDiff line numberDiff line change
@@ -75,7 +75,9 @@ $defs:
7575
bias-pull-down: true
7676
bias-pull-up: true
7777
bias-disable: true
78-
input-enable: true
78+
input-enable: false
79+
output-disable: true
80+
output-enable: true
7981
output-high: true
8082
output-low: true
8183

‎MAINTAINERS

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Original file line numberDiff line numberDiff line change
@@ -2604,6 +2604,12 @@ F: include/dt-bindings/*/qcom*
26042604
F: include/linux/*/qcom*
26052605
F: include/linux/soc/qcom/
26062606

2607+
ARM/QUALCOMM CHROMEBOOK SUPPORT
2608+
R: [email protected]
2609+
F: arch/arm64/boot/dts/qcom/sc7180*
2610+
F: arch/arm64/boot/dts/qcom/sc7280*
2611+
F: arch/arm64/boot/dts/qcom/sdm845-cheza*
2612+
26072613
ARM/RDA MICRO ARCHITECTURE
26082614
M: Manivannan Sadhasivam <[email protected]>
26092615
L: [email protected] (moderated for non-subscribers)

‎arch/arm64/boot/dts/qcom/Makefile

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,12 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
44
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
55
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
66
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb
7+
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
78
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
89
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
910
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
1011
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
12+
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb
1113
dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
1214
dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
1315
dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
@@ -71,6 +73,8 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb
7173
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
7274
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
7375
dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
76+
dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb
77+
dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb
7478
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
7579
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb
7680
dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
@@ -172,6 +176,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb
172176
dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb
173177
dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb
174178
dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
179+
dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb
175180
dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb
176181
dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb
177182
dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb
@@ -184,7 +189,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb
184189
dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
185190
dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb
186191
dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb
187-
dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish.dtb
192+
dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-boe.dtb
193+
dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-csot.dtb
188194
dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb
189195
dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb
190196
dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb

‎arch/arm64/boot/dts/qcom/apq8016-sbc.dts

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@@ -729,7 +729,6 @@
729729
function = "gpio";
730730

731731
drive-strength = <8>;
732-
input-enable;
733732
bias-pull-up;
734733
};
735734

@@ -770,7 +769,6 @@
770769
function = "gpio";
771770

772771
drive-strength = <8>;
773-
input-enable;
774772
bias-pull-up;
775773
};
776774
};

‎arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts

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@@ -28,6 +28,13 @@
2828
status = "okay";
2929
};
3030

31+
&blsp1_i2c1 {
32+
clock-frequency = <400000>;
33+
pinctrl-0 = <&i2c_1_pins>;
34+
pinctrl-names = "default";
35+
status = "okay";
36+
};
37+
3138
&sdhc {
3239
bus-width = <4>;
3340
max-frequency = <192000000>;
@@ -50,6 +57,13 @@
5057
/* PINCTRL */
5158

5259
&tlmm {
60+
i2c_1_pins: i2c-1-state {
61+
pins = "gpio29", "gpio30";
62+
function = "blsp1_i2c0";
63+
drive-strength = <8>;
64+
bias-pull-up;
65+
};
66+
5367
sdc_default_state: sdc-default-state {
5468
clk-pins {
5569
pins = "gpio13";

‎arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts

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@@ -0,0 +1,103 @@
1+
// SPDX-License-Identifier: BSD-3-Clause
2+
/*
3+
* IPQ5332 RDP468 board device tree source
4+
*
5+
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
6+
*/
7+
8+
/dts-v1/;
9+
10+
#include "ipq5332.dtsi"
11+
12+
/ {
13+
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6";
14+
compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";
15+
16+
aliases {
17+
serial0 = &blsp1_uart0;
18+
};
19+
20+
chosen {
21+
stdout-path = "serial0";
22+
};
23+
};
24+
25+
&blsp1_uart0 {
26+
pinctrl-0 = <&serial_0_pins>;
27+
pinctrl-names = "default";
28+
status = "okay";
29+
};
30+
31+
&blsp1_spi0 {
32+
pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
33+
pinctrl-names = "default";
34+
status = "okay";
35+
36+
flash@0 {
37+
compatible = "micron,n25q128a11", "jedec,spi-nor";
38+
reg = <0>;
39+
#address-cells = <1>;
40+
#size-cells = <1>;
41+
spi-max-frequency = <50000000>;
42+
};
43+
};
44+
45+
&sdhc {
46+
bus-width = <4>;
47+
max-frequency = <192000000>;
48+
mmc-ddr-1_8v;
49+
mmc-hs200-1_8v;
50+
non-removable;
51+
pinctrl-0 = <&sdc_default_state>;
52+
pinctrl-names = "default";
53+
status = "okay";
54+
};
55+
56+
&sleep_clk {
57+
clock-frequency = <32000>;
58+
};
59+
60+
&xo_board {
61+
clock-frequency = <24000000>;
62+
};
63+
64+
/* PINCTRL */
65+
66+
&tlmm {
67+
sdc_default_state: sdc-default-state {
68+
clk-pins {
69+
pins = "gpio13";
70+
function = "sdc_clk";
71+
drive-strength = <8>;
72+
bias-disable;
73+
};
74+
75+
cmd-pins {
76+
pins = "gpio12";
77+
function = "sdc_cmd";
78+
drive-strength = <8>;
79+
bias-pull-up;
80+
};
81+
82+
data-pins {
83+
pins = "gpio8", "gpio9", "gpio10", "gpio11";
84+
function = "sdc_data";
85+
drive-strength = <8>;
86+
bias-pull-up;
87+
};
88+
};
89+
90+
spi_0_data_clk_pins: spi-0-data-clk-state {
91+
pins = "gpio14", "gpio15", "gpio16";
92+
function = "blsp0_spi";
93+
drive-strength = <2>;
94+
bias-pull-down;
95+
};
96+
97+
spi_0_cs_pins: spi-0-cs-state {
98+
pins = "gpio17";
99+
function = "blsp0_spi";
100+
drive-strength = <2>;
101+
bias-pull-up;
102+
};
103+
};

‎arch/arm64/boot/dts/qcom/ipq5332.dtsi

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -134,6 +134,13 @@
134134
#size-cells = <1>;
135135
ranges = <0 0 0 0xffffffff>;
136136

137+
rng: rng@e3000 {
138+
compatible = "qcom,prng-ee";
139+
reg = <0x000e3000 0x1000>;
140+
clocks = <&gcc GCC_PRNG_AHB_CLK>;
141+
clock-names = "core";
142+
};
143+
137144
tlmm: pinctrl@1000000 {
138145
compatible = "qcom,ipq5332-tlmm";
139146
reg = <0x01000000 0x300000>;
@@ -191,6 +198,16 @@
191198
status = "disabled";
192199
};
193200

201+
blsp_dma: dma-controller@7884000 {
202+
compatible = "qcom,bam-v1.7.0";
203+
reg = <0x07884000 0x1d000>;
204+
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
205+
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
206+
clock-names = "bam_clk";
207+
#dma-cells = <1>;
208+
qcom,ee = <0>;
209+
};
210+
194211
blsp1_uart0: serial@78af000 {
195212
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
196213
reg = <0x078af000 0x200>;
@@ -201,6 +218,48 @@
201218
status = "disabled";
202219
};
203220

221+
blsp1_spi0: spi@78b5000 {
222+
compatible = "qcom,spi-qup-v2.2.1";
223+
reg = <0x078b5000 0x600>;
224+
#address-cells = <1>;
225+
#size-cells = <0>;
226+
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
227+
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
228+
<&gcc GCC_BLSP1_AHB_CLK>;
229+
clock-names = "core", "iface";
230+
dmas = <&blsp_dma 4>, <&blsp_dma 5>;
231+
dma-names = "tx", "rx";
232+
status = "disabled";
233+
};
234+
235+
blsp1_i2c1: i2c@78b6000 {
236+
compatible = "qcom,i2c-qup-v2.2.1";
237+
reg = <0x078b6000 0x600>;
238+
#address-cells = <1>;
239+
#size-cells = <0>;
240+
interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
241+
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
242+
<&gcc GCC_BLSP1_AHB_CLK>;
243+
clock-names = "core", "iface";
244+
dmas = <&blsp_dma 6>, <&blsp_dma 7>;
245+
dma-names = "tx", "rx";
246+
status = "disabled";
247+
};
248+
249+
blsp1_spi2: spi@78b7000 {
250+
compatible = "qcom,spi-qup-v2.2.1";
251+
reg = <0x078b7000 0x600>;
252+
#address-cells = <1>;
253+
#size-cells = <0>;
254+
interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
255+
clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
256+
<&gcc GCC_BLSP1_AHB_CLK>;
257+
clock-names = "core", "iface";
258+
dmas = <&blsp_dma 8>, <&blsp_dma 9>;
259+
dma-names = "tx", "rx";
260+
status = "disabled";
261+
};
262+
204263
intc: interrupt-controller@b000000 {
205264
compatible = "qcom,msm-qgic2";
206265
reg = <0x0b000000 0x1000>, /* GICD */
@@ -233,6 +292,14 @@
233292
};
234293
};
235294

295+
watchdog: watchdog@b017000 {
296+
compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";
297+
reg = <0x0b017000 0x1000>;
298+
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
299+
clocks = <&sleep_clk>;
300+
timeout-sec = <30>;
301+
};
302+
236303
apcs_glb: mailbox@b111000 {
237304
compatible = "qcom,ipq5332-apcs-apps-global",
238305
"qcom,ipq6018-apcs-apps-global";

‎arch/arm64/boot/dts/qcom/ipq8074.dtsi

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -686,7 +686,8 @@
686686
};
687687

688688
apcs_glb: mailbox@b111000 {
689-
compatible = "qcom,ipq8074-apcs-apps-global";
689+
compatible = "qcom,ipq8074-apcs-apps-global",
690+
"qcom,ipq6018-apcs-apps-global";
690691
reg = <0x0b111000 0x1000>;
691692
clocks = <&a53pll>, <&xo>;
692693
clock-names = "pll", "xo";

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