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Merge tag 'powerpc-5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc updates from Michael Ellerman: "A pretty small batch for us, and apologies for it being a bit late, I wanted to sneak Christophe's user_access_begin() series in. Summary: - Implement user_access_begin() and friends for our platforms that support controlling kernel access to userspace. - Enable CONFIG_VMAP_STACK on 32-bit Book3S and 8xx. - Some tweaks to our pseries IOMMU code to allow SVMs ("secure" virtual machines) to use the IOMMU. - Add support for CLOCK_{REALTIME/MONOTONIC}_COARSE to the 32-bit VDSO, and some other improvements. - A series to use the PCI hotplug framework to control opencapi card's so that they can be reset and re-read after flashing a new FPGA image. As well as other minor fixes and improvements as usual. Thanks to: Alastair D'Silva, Alexandre Ghiti, Alexey Kardashevskiy, Andrew Donnellan, Aneesh Kumar K.V, Anju T Sudhakar, Bai Yingjie, Chen Zhou, Christophe Leroy, Frederic Barrat, Greg Kurz, Jason A. Donenfeld, Joel Stanley, Jordan Niethe, Julia Lawall, Krzysztof Kozlowski, Laurent Dufour, Laurentiu Tudor, Linus Walleij, Michael Bringmann, Nathan Chancellor, Nicholas Piggin, Nick Desaulniers, Oliver O'Halloran, Peter Ujfalusi, Pingfan Liu, Ram Pai, Randy Dunlap, Russell Currey, Sam Bobroff, Sebastian Andrzej Siewior, Shawn Anastasio, Stephen Rothwell, Steve Best, Sukadev Bhattiprolu, Thiago Jung Bauermann, Tyrel Datwyler, Vaibhav Jain" * tag 'powerpc-5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (131 commits) powerpc: configs: Cleanup old Kconfig options powerpc/configs/skiroot: Enable some more hardening options powerpc/configs/skiroot: Disable xmon default & enable reboot on panic powerpc/configs/skiroot: Enable security features powerpc/configs/skiroot: Update for symbol movement only powerpc/configs/skiroot: Drop default n CONFIG_CRYPTO_ECHAINIV powerpc/configs/skiroot: Drop HID_LOGITECH powerpc/configs: Drop NET_VENDOR_HP which moved to staging powerpc/configs: NET_CADENCE became NET_VENDOR_CADENCE powerpc/configs: Drop CONFIG_QLGE which moved to staging powerpc: Do not consider weak unresolved symbol relocations as bad powerpc/32s: Fix kasan_early_hash_table() for CONFIG_VMAP_STACK powerpc: indent to improve Kconfig readability powerpc: Provide initial documentation for PAPR hcalls powerpc: Implement user_access_save() and user_access_restore() powerpc: Implement user_access_begin and friends powerpc/32s: Prepare prevent_user_access() for user_access_end() powerpc/32s: Drop NULL addr verification powerpc/kuap: Fix set direction in allow/prevent_user_access() powerpc/32s: Fix bad_kuap_fault() ...
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‎Documentation/devicetree/bindings/spi/fsl-spi.txt

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@@ -15,13 +15,13 @@ Required properties:
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- clock-frequency : input clock frequency to non FSL_SOC cores
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Optional properties:
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- gpios : specifies the gpio pins to be used for chipselects.
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- cs-gpios : specifies the gpio pins to be used for chipselects.
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The gpios will be referred to as reg = <index> in the SPI child nodes.
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If unspecified, a single SPI device without a chip select can be used.
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- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
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SPISEL_BOOT signal is used as chip select for a slave device. Use
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reg = <number of gpios> in the corresponding child node, i.e. 0 if
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the gpios property is not present.
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the cs-gpios property is not present.
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Example:
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spi@4c0 {
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interrupts = <82 0>;
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interrupt-parent = <700>;
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mode = "cpu";
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gpios = <&gpio 18 1 // device reg=<0>
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&gpio 19 1>; // device reg=<1>
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cs-gpios = <&gpio 18 1 // device reg=<0>
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&gpio 19 1>; // device reg=<1>
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};
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‎Documentation/powerpc/imc.rst

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.. SPDX-License-Identifier: GPL-2.0
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.. _imc:
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===================================
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IMC (In-Memory Collection Counters)
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===================================
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Anju T Sudhakar, 10 May 2019
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.. contents::
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:depth: 3
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Basic overview
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==============
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IMC (In-Memory collection counters) is a hardware monitoring facility that
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collects large numbers of hardware performance events at Nest level (these are
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on-chip but off-core), Core level and Thread level.
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The Nest PMU counters are handled by a Nest IMC microcode which runs in the OCC
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(On-Chip Controller) complex. The microcode collects the counter data and moves
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the nest IMC counter data to memory.
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The Core and Thread IMC PMU counters are handled in the core. Core level PMU
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counters give us the IMC counters' data per core and thread level PMU counters
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give us the IMC counters' data per CPU thread.
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OPAL obtains the IMC PMU and supported events information from the IMC Catalog
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and passes on to the kernel via the device tree. The event's information
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contains:
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- Event name
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- Event Offset
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- Event description
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and possibly also:
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- Event scale
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- Event unit
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Some PMUs may have a common scale and unit values for all their supported
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events. For those cases, the scale and unit properties for those events must be
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inherited from the PMU.
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The event offset in the memory is where the counter data gets accumulated.
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IMC catalog is available at:
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https://github.com/open-power/ima-catalog
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The kernel discovers the IMC counters information in the device tree at the
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`imc-counters` device node which has a compatible field
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`ibm,opal-in-memory-counters`. From the device tree, the kernel parses the PMUs
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and their event's information and register the PMU and its attributes in the
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kernel.
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IMC example usage
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=================
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.. code-block:: sh
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# perf list
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[...]
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nest_mcs01/PM_MCS01_64B_RD_DISP_PORT01/ [Kernel PMU event]
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nest_mcs01/PM_MCS01_64B_RD_DISP_PORT23/ [Kernel PMU event]
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[...]
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core_imc/CPM_0THRD_NON_IDLE_PCYC/ [Kernel PMU event]
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core_imc/CPM_1THRD_NON_IDLE_INST/ [Kernel PMU event]
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[...]
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thread_imc/CPM_0THRD_NON_IDLE_PCYC/ [Kernel PMU event]
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thread_imc/CPM_1THRD_NON_IDLE_INST/ [Kernel PMU event]
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To see per chip data for nest_mcs0/PM_MCS_DOWN_128B_DATA_XFER_MC0/:
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.. code-block:: sh
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# ./perf stat -e "nest_mcs01/PM_MCS01_64B_WR_DISP_PORT01/" -a --per-socket
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To see non-idle instructions for core 0:
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.. code-block:: sh
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# ./perf stat -e "core_imc/CPM_NON_IDLE_INST/" -C 0 -I 1000
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To see non-idle instructions for a "make":
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.. code-block:: sh
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# ./perf stat -e "thread_imc/CPM_NON_IDLE_PCYC/" make
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IMC Trace-mode
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===============
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POWER9 supports two modes for IMC which are the Accumulation mode and Trace
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mode. In Accumulation mode, event counts are accumulated in system Memory.
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Hypervisor then reads the posted counts periodically or when requested. In IMC
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Trace mode, the 64 bit trace SCOM value is initialized with the event
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information. The CPMCxSEL and CPMC_LOAD in the trace SCOM, specifies the event
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to be monitored and the sampling duration. On each overflow in the CPMCxSEL,
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hardware snapshots the program counter along with event counts and writes into
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memory pointed by LDBAR.
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LDBAR is a 64 bit special purpose per thread register, it has bits to indicate
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whether hardware is configured for accumulation or trace mode.
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LDBAR Register Layout
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---------------------
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+-------+----------------------+
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| 0 | Enable/Disable |
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+-------+----------------------+
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| 1 | 0: Accumulation Mode |
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| +----------------------+
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| | 1: Trace Mode |
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+-------+----------------------+
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| 2:3 | Reserved |
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+-------+----------------------+
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| 4-6 | PB scope |
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+-------+----------------------+
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| 7 | Reserved |
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+-------+----------------------+
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| 8:50 | Counter Address |
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+-------+----------------------+
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| 51:63 | Reserved |
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+-------+----------------------+
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TRACE_IMC_SCOM bit representation
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---------------------------------
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+-------+------------+
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| 0:1 | SAMPSEL |
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+-------+------------+
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| 2:33 | CPMC_LOAD |
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+-------+------------+
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| 34:40 | CPMC1SEL |
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+-------+------------+
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| 41:47 | CPMC2SEL |
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+-------+------------+
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| 48:50 | BUFFERSIZE |
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+-------+------------+
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| 51:63 | RESERVED |
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+-------+------------+
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CPMC_LOAD contains the sampling duration. SAMPSEL and CPMCxSEL determines the
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event to count. BUFFERSIZE indicates the memory range. On each overflow,
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hardware snapshots the program counter along with event counts and updates the
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memory and reloads the CMPC_LOAD value for the next sampling duration. IMC
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hardware does not support exceptions, so it quietly wraps around if memory
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buffer reaches the end.
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*Currently the event monitored for trace-mode is fixed as cycle.*
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Trace IMC example usage
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=======================
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.. code-block:: sh
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# perf list
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[....]
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trace_imc/trace_cycles/ [Kernel PMU event]
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To record an application/process with trace-imc event:
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.. code-block:: sh
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# perf record -e trace_imc/trace_cycles/ yes > /dev/null
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[ perf record: Woken up 1 times to write data ]
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[ perf record: Captured and wrote 0.012 MB perf.data (21 samples) ]
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The `perf.data` generated, can be read using perf report.
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Benefits of using IMC trace-mode
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================================
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PMI (Performance Monitoring Interrupts) interrupt handling is avoided, since IMC
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trace mode snapshots the program counter and updates to the memory. And this
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also provide a way for the operating system to do instruction sampling in real
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time without PMI processing overhead.
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Performance data using `perf top` with and without trace-imc event.
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PMI interrupts count when `perf top` command is executed without trace-imc event.
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.. code-block:: sh
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# grep PMI /proc/interrupts
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PMI: 0 0 0 0 Performance monitoring interrupts
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# ./perf top
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...
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# grep PMI /proc/interrupts
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PMI: 39735 8710 17338 17801 Performance monitoring interrupts
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# ./perf top -e trace_imc/trace_cycles/
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...
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# grep PMI /proc/interrupts
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PMI: 39735 8710 17338 17801 Performance monitoring interrupts
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That is, the PMI interrupt counts do not increment when using the `trace_imc` event.

‎Documentation/powerpc/index.rst

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elfnote
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firmware-assisted-dump
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hvcs
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imc
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isa-versions
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kaslr-booke32
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mpc52xx
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papr_hcalls
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pci_iov_resource_on_powernv
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pmu-ebb
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ptrace

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