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Fudong Wangalexdeucher
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drm/amd/display: Add smu write msg id fail retry process
A benchmark stress test (12-40 machines x 48hours) found that DCN315 has cases where DC writes to an indirect register to set the smu clock msg id, but when we go to read the same indirect register the returned msg id doesn't match with what we just set it to. So, to fix this retry the write until the register's value matches with the requested value. Cc: [email protected] # 6.1+ Fixes: f949039 ("drm/amd/display: Add DCN315 CLK_MGR") Reviewed-by: Charlene Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Fudong Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@
3232

3333
#define MAX_INSTANCE 6
3434
#define MAX_SEGMENT 6
35+
#define SMU_REGISTER_WRITE_RETRY_COUNT 5
3536

3637
struct IP_BASE_INSTANCE {
3738
unsigned int segment[MAX_SEGMENT];
@@ -132,6 +133,8 @@ static int dcn315_smu_send_msg_with_param(
132133
unsigned int msg_id, unsigned int param)
133134
{
134135
uint32_t result;
136+
uint32_t i = 0;
137+
uint32_t read_back_data;
135138

136139
result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
137140

@@ -148,10 +151,19 @@ static int dcn315_smu_send_msg_with_param(
148151
/* Set the parameter register for the SMU message, unit is Mhz */
149152
REG_WRITE(MP1_SMN_C2PMSG_37, param);
150153

151-
/* Trigger the message transaction by writing the message ID */
152-
generic_write_indirect_reg(CTX,
153-
REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
154-
mmMP1_C2PMSG_3, msg_id);
154+
for (i = 0; i < SMU_REGISTER_WRITE_RETRY_COUNT; i++) {
155+
/* Trigger the message transaction by writing the message ID */
156+
generic_write_indirect_reg(CTX,
157+
REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
158+
mmMP1_C2PMSG_3, msg_id);
159+
read_back_data = generic_read_indirect_reg(CTX,
160+
REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
161+
mmMP1_C2PMSG_3);
162+
if (read_back_data == msg_id)
163+
break;
164+
udelay(2);
165+
smu_print("SMU msg id write fail %x times. \n", i + 1);
166+
}
155167

156168
result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
157169

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