Skip to content

Commit 7222a1b

Browse files
Mark GrossKAGA-KOKO
Mark Gross
authored and
KAGA-KOKO
committed
x86/speculation: Add SRBDS vulnerability and mitigation documentation
Add documentation for the SRBDS vulnerability and its mitigation. [ bp: Massage. jpoimboe: sysfs table strings. ] Signed-off-by: Mark Gross <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> Reviewed-by: Tony Luck <[email protected]> Reviewed-by: Josh Poimboeuf <[email protected]>
1 parent 7e5b3c2 commit 7222a1b

File tree

2 files changed

+149
-0
lines changed

2 files changed

+149
-0
lines changed

‎Documentation/admin-guide/hw-vuln/index.rst

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,3 +14,4 @@ are configurable at compile, boot or run time.
1414
mds
1515
tsx_async_abort
1616
multihit.rst
17+
special-register-buffer-data-sampling.rst

‎Documentation/admin-guide/hw-vuln/special-register-buffer-data-sampling.rst

Lines changed: 148 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,148 @@
1+
.. SPDX-License-Identifier: GPL-2.0
2+
3+
SRBDS - Special Register Buffer Data Sampling
4+
=============================================
5+
6+
SRBDS is a hardware vulnerability that allows MDS :doc:`mds` techniques to
7+
infer values returned from special register accesses. Special register
8+
accesses are accesses to off core registers. According to Intel's evaluation,
9+
the special register reads that have a security expectation of privacy are
10+
RDRAND, RDSEED and SGX EGETKEY.
11+
12+
When RDRAND, RDSEED and EGETKEY instructions are used, the data is moved
13+
to the core through the special register mechanism that is susceptible
14+
to MDS attacks.
15+
16+
Affected processors
17+
--------------------
18+
Core models (desktop, mobile, Xeon-E3) that implement RDRAND and/or RDSEED may
19+
be affected.
20+
21+
A processor is affected by SRBDS if its Family_Model and stepping is
22+
in the following list, with the exception of the listed processors
23+
exporting MDS_NO while Intel TSX is available yet not enabled. The
24+
latter class of processors are only affected when Intel TSX is enabled
25+
by software using TSX_CTRL_MSR otherwise they are not affected.
26+
27+
============= ============ ========
28+
common name Family_Model Stepping
29+
============= ============ ========
30+
Haswell 06_3CH All
31+
Haswell_L 06_45H All
32+
Haswell_G 06_46H All
33+
34+
Broadwell_G 06_47H All
35+
Broadwell 06_3DH All
36+
37+
Skylake_L 06_4EH All
38+
Skylake 06_5EH All
39+
40+
Kabylake_L 06_8EH <=0xC
41+
42+
Kabylake 06_9EH <=0xD
43+
============= ============ ========
44+
45+
Related CVEs
46+
------------
47+
48+
The following CVE entry is related to this SRBDS issue:
49+
50+
============== ===== =====================================
51+
CVE-2020-0543 SRBDS Special Register Buffer Data Sampling
52+
============== ===== =====================================
53+
54+
Attack scenarios
55+
----------------
56+
An unprivileged user can extract values returned from RDRAND and RDSEED
57+
executed on another core or sibling thread using MDS techniques.
58+
59+
60+
Mitigation mechanism
61+
-------------------
62+
Intel will release microcode updates that modify the RDRAND, RDSEED, and
63+
EGETKEY instructions to overwrite secret special register data in the shared
64+
staging buffer before the secret data can be accessed by another logical
65+
processor.
66+
67+
During execution of the RDRAND, RDSEED, or EGETKEY instructions, off-core
68+
accesses from other logical processors will be delayed until the special
69+
register read is complete and the secret data in the shared staging buffer is
70+
overwritten.
71+
72+
This has three effects on performance:
73+
74+
#. RDRAND, RDSEED, or EGETKEY instructions have higher latency.
75+
76+
#. Executing RDRAND at the same time on multiple logical processors will be
77+
serialized, resulting in an overall reduction in the maximum RDRAND
78+
bandwidth.
79+
80+
#. Executing RDRAND, RDSEED or EGETKEY will delay memory accesses from other
81+
logical processors that miss their core caches, with an impact similar to
82+
legacy locked cache-line-split accesses.
83+
84+
The microcode updates provide an opt-out mechanism (RNGDS_MITG_DIS) to disable
85+
the mitigation for RDRAND and RDSEED instructions executed outside of Intel
86+
Software Guard Extensions (Intel SGX) enclaves. On logical processors that
87+
disable the mitigation using this opt-out mechanism, RDRAND and RDSEED do not
88+
take longer to execute and do not impact performance of sibling logical
89+
processors memory accesses. The opt-out mechanism does not affect Intel SGX
90+
enclaves (including execution of RDRAND or RDSEED inside an enclave, as well
91+
as EGETKEY execution).
92+
93+
IA32_MCU_OPT_CTRL MSR Definition
94+
--------------------------------
95+
Along with the mitigation for this issue, Intel added a new thread-scope
96+
IA32_MCU_OPT_CTRL MSR, (address 0x123). The presence of this MSR and
97+
RNGDS_MITG_DIS (bit 0) is enumerated by CPUID.(EAX=07H,ECX=0).EDX[SRBDS_CTRL =
98+
9]==1. This MSR is introduced through the microcode update.
99+
100+
Setting IA32_MCU_OPT_CTRL[0] (RNGDS_MITG_DIS) to 1 for a logical processor
101+
disables the mitigation for RDRAND and RDSEED executed outside of an Intel SGX
102+
enclave on that logical processor. Opting out of the mitigation for a
103+
particular logical processor does not affect the RDRAND and RDSEED mitigations
104+
for other logical processors.
105+
106+
Note that inside of an Intel SGX enclave, the mitigation is applied regardless
107+
of the value of RNGDS_MITG_DS.
108+
109+
Mitigation control on the kernel command line
110+
---------------------------------------------
111+
The kernel command line allows control over the SRBDS mitigation at boot time
112+
with the option "srbds=". The option for this is:
113+
114+
============= =============================================================
115+
off This option disables SRBDS mitigation for RDRAND and RDSEED on
116+
affected platforms.
117+
============= =============================================================
118+
119+
SRBDS System Information
120+
-----------------------
121+
The Linux kernel provides vulnerability status information through sysfs. For
122+
SRBDS this can be accessed by the following sysfs file:
123+
/sys/devices/system/cpu/vulnerabilities/srbds
124+
125+
The possible values contained in this file are:
126+
127+
============================== =============================================
128+
Not affected Processor not vulnerable
129+
Vulnerable Processor vulnerable and mitigation disabled
130+
Vulnerable: No microcode Processor vulnerable and microcode is missing
131+
mitigation
132+
Mitigation: Microcode Processor is vulnerable and mitigation is in
133+
effect.
134+
Mitigation: TSX disabled Processor is only vulnerable when TSX is
135+
enabled while this system was booted with TSX
136+
disabled.
137+
Unknown: Dependent on
138+
hypervisor status Running on virtual guest processor that is
139+
affected but with no way to know if host
140+
processor is mitigated or vulnerable.
141+
============================== =============================================
142+
143+
SRBDS Default mitigation
144+
------------------------
145+
This new microcode serializes processor access during execution of RDRAND,
146+
RDSEED ensures that the shared buffer is overwritten before it is released for
147+
reuse. Use the "srbds=off" kernel command line to disable the mitigation for
148+
RDRAND and RDSEED.

0 commit comments

Comments
 (0)