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StanFox1984vsyrjala
StanFox1984
authored and
vsyrjala
committed
drm/i915: Add TGL+ SAGV support
Starting from TGL we need to have a separate wm0 values for SAGV and non-SAGV which affects how calculations are done. v2: Remove long lines v3: Removed COLOR_PLANE enum references v4, v5, v6: Fixed rebase conflict v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville) - Removed sagv_uv_wm0(Ville) - can_sagv->use_sagv_wm(Ville) v8: - Moved tgl_crtc_can_enable_sagv function up(Ville) - Changed comment regarding pipe_wm usage(Ville) - Call intel_can_enable_sagv and tgl_compute_sagv_wm only for Gen12(Ville) - Some sagv debugs removed(Ville) - skl_print_wm_changes improvements(Ville) - Do assignment instead of memcpy in skl_pipe_wm_get_hw_state(Ville) v9: - Removed can_sagv variable(Ville) - Removed spurious line(Ville) - Changed u32 to unsigned int as agreed(Ville) - Assign sagv only for gen12 in skl_pipe_wm_get_hw_state(Ville) Signed-off-by: Stanislav Lisovskiy <[email protected]> [vsyrjala: Remove the dead 'return false' from intel_crtc_can_enable_sagv()] Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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‎drivers/gpu/drm/i915/display/intel_display.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14025,7 +14025,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
1402514025
/* Watermarks */
1402614026
for (level = 0; level <= max_level; level++) {
1402714027
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14028-
&sw_plane_wm->wm[level]))
14028+
&sw_plane_wm->wm[level]) ||
14029+
(level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14030+
&sw_plane_wm->sagv_wm0)))
1402914031
continue;
1403014032

1403114033
drm_err(&dev_priv->drm,
@@ -14080,7 +14082,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
1408014082
/* Watermarks */
1408114083
for (level = 0; level <= max_level; level++) {
1408214084
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14083-
&sw_plane_wm->wm[level]))
14085+
&sw_plane_wm->wm[level]) ||
14086+
(level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14087+
&sw_plane_wm->sagv_wm0)))
1408414088
continue;
1408514089

1408614090
drm_err(&dev_priv->drm,

‎drivers/gpu/drm/i915/display/intel_display_types.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -688,11 +688,13 @@ struct skl_plane_wm {
688688
struct skl_wm_level wm[8];
689689
struct skl_wm_level uv_wm[8];
690690
struct skl_wm_level trans_wm;
691+
struct skl_wm_level sagv_wm0;
691692
bool is_planar;
692693
};
693694

694695
struct skl_pipe_wm {
695696
struct skl_plane_wm planes[I915_MAX_PLANES];
697+
bool use_sagv_wm;
696698
};
697699

698700
enum vlv_wm_level {

‎drivers/gpu/drm/i915/intel_pm.c

Lines changed: 91 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -3853,9 +3853,36 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
38533853
return true;
38543854
}
38553855

3856+
static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3857+
{
3858+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3859+
enum plane_id plane_id;
3860+
3861+
if (!crtc_state->hw.active)
3862+
return true;
3863+
3864+
for_each_plane_id_on_crtc(crtc, plane_id) {
3865+
const struct skl_ddb_entry *plane_alloc =
3866+
&crtc_state->wm.skl.plane_ddb_y[plane_id];
3867+
const struct skl_plane_wm *wm =
3868+
&crtc_state->wm.skl.optimal.planes[plane_id];
3869+
3870+
if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
3871+
return false;
3872+
}
3873+
3874+
return true;
3875+
}
3876+
38563877
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
38573878
{
3858-
return skl_crtc_can_enable_sagv(crtc_state);
3879+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3880+
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3881+
3882+
if (INTEL_GEN(dev_priv) >= 12)
3883+
return tgl_crtc_can_enable_sagv(crtc_state);
3884+
else
3885+
return skl_crtc_can_enable_sagv(crtc_state);
38593886
}
38603887

38613888
bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
@@ -3873,7 +3900,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
38733900
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
38743901
int ret;
38753902
struct intel_crtc *crtc;
3876-
const struct intel_crtc_state *new_crtc_state;
3903+
struct intel_crtc_state *new_crtc_state;
38773904
struct intel_bw_state *new_bw_state = NULL;
38783905
const struct intel_bw_state *old_bw_state = NULL;
38793906
int i;
@@ -3904,6 +3931,20 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
39043931
return ret;
39053932
}
39063933

3934+
for_each_new_intel_crtc_in_state(state, crtc,
3935+
new_crtc_state, i) {
3936+
struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
3937+
3938+
/*
3939+
* We store use_sagv_wm in the crtc state rather than relying on
3940+
* that bw state since we have no convenient way to get at the
3941+
* latter from the plane commit hooks (especially in the legacy
3942+
* cursor case)
3943+
*/
3944+
pipe_wm->use_sagv_wm = INTEL_GEN(dev_priv) >= 12 &&
3945+
intel_can_enable_sagv(dev_priv, new_bw_state);
3946+
}
3947+
39073948
if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
39083949
intel_can_enable_sagv(dev_priv, old_bw_state)) {
39093950
ret = intel_atomic_serialize_global_state(&new_bw_state->base);
@@ -4647,8 +4688,11 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
46474688
enum plane_id plane_id,
46484689
int level)
46494690
{
4650-
const struct skl_plane_wm *wm =
4651-
&crtc_state->wm.skl.optimal.planes[plane_id];
4691+
const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
4692+
const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
4693+
4694+
if (level == 0 && pipe_wm->use_sagv_wm)
4695+
return &wm->sagv_wm0;
46524696

46534697
return &wm->wm[level];
46544698
}
@@ -4689,7 +4733,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
46894733
plane_data_rate,
46904734
uv_plane_data_rate);
46914735

4692-
46934736
skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
46944737
alloc, &num_active);
46954738
alloc_size = skl_ddb_entry_size(alloc);
@@ -5225,6 +5268,20 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
52255268
}
52265269
}
52275270

5271+
static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
5272+
const struct skl_wm_params *wm_params,
5273+
struct skl_plane_wm *plane_wm)
5274+
{
5275+
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5276+
struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0;
5277+
struct skl_wm_level *levels = plane_wm->wm;
5278+
unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;
5279+
5280+
skl_compute_plane_wm(crtc_state, 0, latency,
5281+
wm_params, &levels[0],
5282+
sagv_wm);
5283+
}
5284+
52285285
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
52295286
const struct skl_wm_params *wp,
52305287
struct skl_plane_wm *wm)
@@ -5292,6 +5349,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
52925349
const struct intel_plane_state *plane_state,
52935350
enum plane_id plane_id, int color_plane)
52945351
{
5352+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5353+
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
52955354
struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
52965355
struct skl_wm_params wm_params;
52975356
int ret;
@@ -5302,6 +5361,10 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
53025361
return ret;
53035362

53045363
skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
5364+
5365+
if (INTEL_GEN(dev_priv) >= 12)
5366+
tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
5367+
53055368
skl_compute_transition_wm(crtc_state, &wm_params, wm);
53065369

53075370
return 0;
@@ -5668,23 +5731,25 @@ skl_print_wm_changes(struct intel_atomic_state *state)
56685731
continue;
56695732

56705733
drm_dbg_kms(&dev_priv->drm,
5671-
"[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm"
5672-
" -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm\n",
5734+
"[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm"
5735+
" -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm\n",
56735736
plane->base.base.id, plane->base.name,
56745737
enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
56755738
enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
56765739
enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
56775740
enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
56785741
enast(old_wm->trans_wm.plane_en),
5742+
enast(old_wm->sagv_wm0.plane_en),
56795743
enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
56805744
enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
56815745
enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
56825746
enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
5683-
enast(new_wm->trans_wm.plane_en));
5747+
enast(new_wm->trans_wm.plane_en),
5748+
enast(new_wm->sagv_wm0.plane_en));
56845749

56855750
drm_dbg_kms(&dev_priv->drm,
5686-
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
5687-
" -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
5751+
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
5752+
" -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
56885753
plane->base.base.id, plane->base.name,
56895754
enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
56905755
enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
@@ -5695,6 +5760,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
56955760
enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
56965761
enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
56975762
enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
5763+
enast(old_wm->sagv_wm0.ignore_lines), old_wm->sagv_wm0.plane_res_l,
56985764

56995765
enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
57005766
enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
@@ -5704,37 +5770,42 @@ skl_print_wm_changes(struct intel_atomic_state *state)
57045770
enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
57055771
enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
57065772
enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
5707-
enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
5773+
enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l,
5774+
enast(new_wm->sagv_wm0.ignore_lines), new_wm->sagv_wm0.plane_res_l);
57085775

57095776
drm_dbg_kms(&dev_priv->drm,
5710-
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5711-
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
5777+
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5778+
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
57125779
plane->base.base.id, plane->base.name,
57135780
old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
57145781
old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
57155782
old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
57165783
old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
57175784
old_wm->trans_wm.plane_res_b,
5785+
old_wm->sagv_wm0.plane_res_b,
57185786
new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
57195787
new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
57205788
new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
57215789
new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
5722-
new_wm->trans_wm.plane_res_b);
5790+
new_wm->trans_wm.plane_res_b,
5791+
new_wm->sagv_wm0.plane_res_b);
57235792

57245793
drm_dbg_kms(&dev_priv->drm,
5725-
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5726-
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
5794+
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5795+
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
57275796
plane->base.base.id, plane->base.name,
57285797
old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
57295798
old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
57305799
old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
57315800
old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
57325801
old_wm->trans_wm.min_ddb_alloc,
5802+
old_wm->sagv_wm0.min_ddb_alloc,
57335803
new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
57345804
new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
57355805
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
57365806
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
5737-
new_wm->trans_wm.min_ddb_alloc);
5807+
new_wm->trans_wm.min_ddb_alloc,
5808+
new_wm->sagv_wm0.min_ddb_alloc);
57385809
}
57395810
}
57405811
}
@@ -6027,6 +6098,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
60276098
skl_wm_level_from_reg_val(val, &wm->wm[level]);
60286099
}
60296100

6101+
if (INTEL_GEN(dev_priv) >= 12)
6102+
wm->sagv_wm0 = wm->wm[0];
6103+
60306104
if (plane_id != PLANE_CURSOR)
60316105
val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
60326106
else

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