Skip to content

Commit 72455e3

Browse files
TE-N-ShengjiuWangbroonie
authored andcommitted
ASoC: fsl_sai: Enable 'FIFO continue on error' FCONT bit
FCONT=1 means On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. Set FCONT bit in control register to avoid the channel swap issue after SAI xrun. Signed-off-by: Shengjiu Wang <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Mark Brown <[email protected]>
1 parent a36614b commit 72455e3

File tree

2 files changed

+5
-1
lines changed

2 files changed

+5
-1
lines changed

sound/soc/fsl/fsl_sai.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -613,6 +613,9 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
613613

614614
val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
615615

616+
/* Set to avoid channel swap */
617+
val_cr4 |= FSL_SAI_CR4_FCONT;
618+
616619
/* Set to output mode to avoid tri-stated data pins */
617620
if (tx)
618621
val_cr4 |= FSL_SAI_CR4_CHMOD;
@@ -699,7 +702,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
699702

700703
regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
701704
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
702-
FSL_SAI_CR4_CHMOD_MASK,
705+
FSL_SAI_CR4_CHMOD_MASK | FSL_SAI_CR4_FCONT_MASK,
703706
val_cr4);
704707
regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
705708
FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |

sound/soc/fsl/fsl_sai.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -137,6 +137,7 @@
137137

138138
/* SAI Transmit and Receive Configuration 4 Register */
139139

140+
#define FSL_SAI_CR4_FCONT_MASK BIT(28)
140141
#define FSL_SAI_CR4_FCONT BIT(28)
141142
#define FSL_SAI_CR4_FCOMB_SHIFT BIT(26)
142143
#define FSL_SAI_CR4_FCOMB_SOFT BIT(27)

0 commit comments

Comments
 (0)