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Nicholas Kazlauskasalexdeucher
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drm/amd/display: Guard against setting dispclk low when active
[Why] We should never apply a minimum dispclk value while in prepare_bandwidth or while displays are active. This is always an optimization for when all displays are disabled. [How] Defer dispclk optimization until safe_to_lower = true and display_count reaches 0. Since 0 has a special value in this logic (ie. no dispclk required) we also need adjust the logic that clamps it for the actual request to PMFW. Reviewed-by: Gabe Teeger <[email protected]> Reviewed-by: Leo Chen <[email protected]> Reviewed-by: Syed Hassan <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -467,14 +467,19 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
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update_dppclk = true;
468468
}
469469

470-
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
470+
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) &&
471+
(new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) {
472+
int requested_dispclk_khz = new_clocks->dispclk_khz;
473+
471474
dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
472475

473-
if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz)
474-
new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz;
476+
/* Clamp the requested clock to PMFW based on their limit. */
477+
if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)
478+
requested_dispclk_khz = dc->debug.min_disp_clk_khz;
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480+
dcn35_smu_set_dispclk(clk_mgr, requested_dispclk_khz);
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clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
477-
dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
482+
478483
dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
479484

480485
update_dispclk = true;

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