|
28 | 28 | #define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 26
|
29 | 29 | #define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15
|
30 | 30 | #define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15
|
31 |
| -#define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS 15 |
32 | 31 | #define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS 15
|
33 |
| -#define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS 15 |
34 | 32 | #define RTL8723B_TRANS_ACT_TO_LPS_STEPS 15
|
35 | 33 | #define RTL8723B_TRANS_LPS_TO_ACT_STEPS 15
|
36 | 34 | #define RTL8723B_TRANS_ACT_TO_SWLPS_STEPS 22
|
|
128 | 126 | {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
129 | 127 | {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
130 | 128 |
|
131 |
| -#define RTL8723B_TRANS_PDN_TO_CARDEMU \ |
132 |
| - /* format */ \ |
133 |
| - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ |
134 |
| - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ |
135 |
| - |
136 | 129 | #define RTL8723B_TRANS_ACT_TO_LPS \
|
137 | 130 | /* format */ \
|
138 | 131 | /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
|
0 commit comments