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vsyrjalavsyrjala
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drm/i915/dpio: s/port/ch/
Stop calling the DPIO PHY channel "port". Just say "ch", which is already used in a bunch of places. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
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-49
lines changed

2 files changed

+49
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lines changed

‎drivers/gpu/drm/i915/display/intel_dpio_phy.c

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1069,23 +1069,23 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
10691069
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10701070
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
10711071
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1072-
enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1072+
enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
10731073
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
10741074

10751075
vlv_dpio_get(dev_priv);
10761076

1077-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), 0x00000000);
1078-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(port), demph_reg_value);
1079-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(port),
1077+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x00000000);
1078+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
1079+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
10801080
uniqtranscale_reg_value);
1081-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(port), 0x0C782040);
1081+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
10821082

10831083
if (tx3_demph)
1084-
vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(port), tx3_demph);
1084+
vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
10851085

1086-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(port), 0x00030000);
1087-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(port), preemph_reg_value);
1088-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1086+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x00030000);
1087+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
1088+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
10891089

10901090
vlv_dpio_put(dev_priv);
10911091
}
@@ -1096,25 +1096,25 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
10961096
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
10971097
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10981098
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1099-
enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1099+
enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
11001100
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
11011101

11021102
/* Program Tx lane resets to default */
11031103
vlv_dpio_get(dev_priv);
11041104

1105-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port),
1105+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
11061106
DPIO_PCS_TX_LANE2_RESET |
11071107
DPIO_PCS_TX_LANE1_RESET);
1108-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port),
1108+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
11091109
DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
11101110
DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
11111111
(1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
11121112
DPIO_PCS_CLK_SOFT_RESET);
11131113

11141114
/* Fix up inter-pair skew failure */
1115-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(port), 0x00750f00);
1116-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(port), 0x00001500);
1117-
vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(port), 0x40400000);
1115+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(ch), 0x00750f00);
1116+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(ch), 0x00001500);
1117+
vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(ch), 0x40400000);
11181118

11191119
vlv_dpio_put(dev_priv);
11201120
}
@@ -1126,7 +1126,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
11261126
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
11271127
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11281128
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1129-
enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1129+
enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
11301130
enum pipe pipe = crtc->pipe;
11311131
enum dpio_phy phy = vlv_pipe_to_phy(pipe);
11321132
u32 val;
@@ -1140,11 +1140,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
11401140
else
11411141
val &= ~(1<<21);
11421142
val |= 0x001000c4;
1143-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(port), val);
1143+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val);
11441144

11451145
/* Program lane clock */
1146-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(port), 0x00760018);
1147-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(port), 0x00400888);
1146+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(ch), 0x00760018);
1147+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(ch), 0x00400888);
11481148

11491149
vlv_dpio_put(dev_priv);
11501150
}
@@ -1155,11 +1155,11 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
11551155
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
11561156
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11571157
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1158-
enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1158+
enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
11591159
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
11601160

11611161
vlv_dpio_get(dev_priv);
1162-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port), 0x00000000);
1163-
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port), 0x00e00060);
1162+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), 0x00000000);
1163+
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch), 0x00e00060);
11641164
vlv_dpio_put(dev_priv);
11651165
}

‎drivers/gpu/drm/i915/display/intel_dpll.c

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -539,7 +539,7 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
539539
{
540540
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
541541
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
542-
enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe);
542+
enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
543543
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
544544
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
545545
struct dpll clock;
@@ -551,11 +551,11 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
551551
return;
552552

553553
vlv_dpio_get(dev_priv);
554-
cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(port));
555-
pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(port));
556-
pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(port));
557-
pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(port));
558-
pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
554+
cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(ch));
555+
pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(ch));
556+
pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(ch));
557+
pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(ch));
558+
pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch));
559559
vlv_dpio_put(dev_priv);
560560

561561
clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
@@ -2027,7 +2027,7 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
20272027
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
20282028
const struct dpll *clock = &crtc_state->dpll;
20292029
enum pipe pipe = crtc->pipe;
2030-
enum dpio_channel port = vlv_pipe_to_channel(pipe);
2030+
enum dpio_channel ch = vlv_pipe_to_channel(pipe);
20312031
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
20322032
u32 tmp, loopfilter, tribuf_calcntr;
20332033
u32 m2_frac;
@@ -2038,41 +2038,41 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
20382038
vlv_dpio_get(dev_priv);
20392039

20402040
/* p1 and p2 divider */
2041-
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port),
2041+
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(ch),
20422042
5 << DPIO_CHV_S1_DIV_SHIFT |
20432043
clock->p1 << DPIO_CHV_P1_DIV_SHIFT |
20442044
clock->p2 << DPIO_CHV_P2_DIV_SHIFT |
20452045
1 << DPIO_CHV_K_DIV_SHIFT);
20462046

20472047
/* Feedback post-divider - m2 */
2048-
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port),
2048+
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(ch),
20492049
clock->m2 >> 22);
20502050

20512051
/* Feedback refclk divider - n and m1 */
2052-
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port),
2052+
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(ch),
20532053
DPIO_CHV_M1_DIV_BY_2 |
20542054
1 << DPIO_CHV_N_DIV_SHIFT);
20552055

20562056
/* M2 fraction division */
2057-
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port),
2057+
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(ch),
20582058
m2_frac);
20592059

20602060
/* M2 fraction division enable */
2061-
tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
2061+
tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch));
20622062
tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
20632063
tmp |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
20642064
if (m2_frac)
20652065
tmp |= DPIO_CHV_FRAC_DIV_EN;
2066-
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), tmp);
2066+
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(ch), tmp);
20672067

20682068
/* Program digital lock detect threshold */
2069-
tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port));
2069+
tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(ch));
20702070
tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
20712071
DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
20722072
tmp |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
20732073
if (!m2_frac)
20742074
tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
2075-
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), tmp);
2075+
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(ch), tmp);
20762076

20772077
/* Loop filter */
20782078
if (clock->vco == 5400000) {
@@ -2097,17 +2097,17 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
20972097
loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
20982098
tribuf_calcntr = 0;
20992099
}
2100-
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(port), loopfilter);
2100+
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(ch), loopfilter);
21012101

2102-
tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port));
2102+
tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(ch));
21032103
tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
21042104
tmp |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
2105-
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), tmp);
2105+
vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(ch), tmp);
21062106

21072107
/* AFC Recal */
2108-
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port),
2109-
vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)) |
2110-
DPIO_AFC_RECAL);
2108+
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch),
2109+
vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)) |
2110+
DPIO_AFC_RECAL);
21112111

21122112
vlv_dpio_put(dev_priv);
21132113
}
@@ -2118,16 +2118,16 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
21182118
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
21192119
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
21202120
enum pipe pipe = crtc->pipe;
2121-
enum dpio_channel port = vlv_pipe_to_channel(pipe);
2121+
enum dpio_channel ch = vlv_pipe_to_channel(pipe);
21222122
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
21232123
u32 tmp;
21242124

21252125
vlv_dpio_get(dev_priv);
21262126

21272127
/* Enable back the 10bit clock to display controller */
2128-
tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port));
2128+
tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch));
21292129
tmp |= DPIO_DCLKP_EN;
2130-
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), tmp);
2130+
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), tmp);
21312131

21322132
vlv_dpio_put(dev_priv);
21332133

@@ -2246,7 +2246,7 @@ void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
22462246

22472247
void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
22482248
{
2249-
enum dpio_channel port = vlv_pipe_to_channel(pipe);
2249+
enum dpio_channel ch = vlv_pipe_to_channel(pipe);
22502250
enum dpio_phy phy = vlv_pipe_to_phy(pipe);
22512251
u32 val;
22522252

@@ -2264,9 +2264,9 @@ void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
22642264
vlv_dpio_get(dev_priv);
22652265

22662266
/* Disable 10bit clock to display controller */
2267-
val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port));
2267+
val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch));
22682268
val &= ~DPIO_DCLKP_EN;
2269-
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), val);
2269+
vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), val);
22702270

22712271
vlv_dpio_put(dev_priv);
22722272
}

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