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Merge tag 'qcom-arm32-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm32 DeviceTree updates for v6.16 Introduce support for the AP8064-based LG Nexus 4. MSM8226 is extended with modem-related features, the LTE-capable variant MSM8926 is introduced, and modem support is enabled on Samsung Galaxy Tab 4. Display-related clocks and power-domains are defined for the simple framebuffer of Motorola Moto G, to allow booting without clk_ignore_unused and pd_ignore_unused. On MSM8960 SDCC BAM and thermal sensor (tsens) is introduced. * tag 'qcom-arm32-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: ARM: dts: qcom: apq8064: move replicator out of soc node ARM: dts: qcom: apq8064: use new compatible for SPS SIC device ARM: dts: qcom: apq8064: use new compatible for SFPB device ARM: dts: qcom: apq8064 merge hw splinlock into corresponding syscon device ARM: dts: qcom: apq8064: add missing clocks to the timer node ARM: dts: qcom: apq8064-lg-nexus4-mako: Enable WiFi ARM: dts: qcom: msm8226-motorola-falcon: specify vddio_disp output voltage ARM: dts: qcom: msm8226-motorola-falcon: limit TPS65132 to 5.4V ARM: dts: qcom: msm8226-motorola-falcon: add I2C clock frequencies ARM: dts: qcom: msm8226-motorola-falcon: add clocks, power-domain to simpleFB ARM: dts: qcom: ipq4019: Drop redundant CPU "clock-latency" ARM: dts: qcom: sdx55/sdx65: Fix CPU power-domain-names ARM: dts: qcom: msm8974: Use the header with DSI phy clock IDs ARM: dts: qcom: msm8226: Use the header with DSI phy clock IDs Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 2b18310 + f242003 commit 759dd3f

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8 files changed

+99
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‎arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,15 @@
3131
vsp-supply = <&reg_lcd_pos>;
3232
vsn-supply = <&reg_lcd_neg>;
3333
vddio-supply = <&vddio_disp_vreg>;
34+
clocks = <&mmcc MDSS_AHB_CLK>,
35+
<&mmcc MDSS_AXI_CLK>,
36+
<&mmcc MDSS_BYTE0_CLK>,
37+
<&mmcc MDSS_ESC0_CLK>,
38+
<&mmcc MDSS_MDP_CLK>,
39+
<&mmcc MMSS_MISC_AHB_CLK>,
40+
<&mmcc MDSS_PCLK0_CLK>,
41+
<&mmcc MDSS_VSYNC_CLK>;
42+
power-domains = <&mmcc MDSS_GDSC>;
3443
};
3544
};
3645

@@ -53,9 +62,12 @@
5362
};
5463
};
5564

65+
/* TI TPS22902 */
5666
vddio_disp_vreg: regulator-vddio-disp {
5767
compatible = "regulator-fixed";
5868
regulator-name = "vddio_disp";
69+
regulator-min-microvolt = <1800000>;
70+
regulator-max-microvolt = <1800000>;
5971
gpio = <&tlmm 34 GPIO_ACTIVE_HIGH>;
6072
vin-supply = <&pm8226_l8>;
6173
startup-delay-us = <300>;
@@ -97,6 +109,7 @@
97109
};
98110

99111
&blsp1_i2c2 {
112+
clock-frequency = <100000>;
100113
status = "okay";
101114

102115
magnetometer@c {
@@ -126,6 +139,7 @@
126139
};
127140

128141
&blsp1_i2c3 {
142+
clock-frequency = <400000>;
129143
status = "okay";
130144

131145
regulator@3e {
@@ -136,17 +150,17 @@
136150

137151
reg_lcd_pos: outp {
138152
regulator-name = "outp";
139-
regulator-min-microvolt = <4000000>;
140-
regulator-max-microvolt = <6000000>;
153+
regulator-min-microvolt = <5400000>;
154+
regulator-max-microvolt = <5400000>;
141155
regulator-active-discharge = <1>;
142156
regulator-boot-on;
143157
enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
144158
};
145159

146160
reg_lcd_neg: outn {
147161
regulator-name = "outn";
148-
regulator-min-microvolt = <4000000>;
149-
regulator-max-microvolt = <6000000>;
162+
regulator-min-microvolt = <5400000>;
163+
regulator-max-microvolt = <5400000>;
150164
regulator-active-discharge = <1>;
151165
regulator-boot-on;
152166
enable-gpios = <&tlmm 33 GPIO_ACTIVE_HIGH>;

‎arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,24 @@
8686
status = "okay";
8787
};
8888

89+
&riva {
90+
pinctrl-names = "default";
91+
pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>;
92+
93+
vddcx-supply = <&pm8921_s3>;
94+
vddmx-supply = <&pm8921_l24>;
95+
vddpx-supply = <&pm8921_s4>;
96+
97+
status = "okay";
98+
99+
iris {
100+
vddxo-supply = <&pm8921_l4>;
101+
vddrfa-supply = <&pm8921_s2>;
102+
vddpa-supply = <&pm8921_l10>;
103+
vdddig-supply = <&pm8921_lvs2>;
104+
};
105+
};
106+
89107
&rpm {
90108
regulators {
91109
compatible = "qcom,rpm-pm8921-regulators";

‎arch/arm/boot/dts/qcom/qcom-apq8064.dtsi

Lines changed: 43 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -213,12 +213,6 @@
213213
};
214214
};
215215

216-
sfpb_mutex: hwmutex {
217-
compatible = "qcom,sfpb-mutex";
218-
syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
219-
#hwlock-cells = <1>;
220-
};
221-
222216
smem {
223217
compatible = "qcom,smem";
224218
memory-region = <&smem_region>;
@@ -284,6 +278,40 @@
284278
};
285279
};
286280

281+
replicator {
282+
compatible = "arm,coresight-static-replicator";
283+
284+
clocks = <&rpmcc RPM_QDSS_CLK>;
285+
clock-names = "apb_pclk";
286+
287+
in-ports {
288+
port {
289+
replicator_in: endpoint {
290+
remote-endpoint = <&funnel_out>;
291+
};
292+
};
293+
};
294+
295+
out-ports {
296+
#address-cells = <1>;
297+
#size-cells = <0>;
298+
299+
port@0 {
300+
reg = <0>;
301+
replicator_out0: endpoint {
302+
remote-endpoint = <&etb_in>;
303+
};
304+
};
305+
306+
port@1 {
307+
reg = <1>;
308+
replicator_out1: endpoint {
309+
remote-endpoint = <&tpiu_in>;
310+
};
311+
};
312+
};
313+
};
314+
287315
soc: soc {
288316
#address-cells = <1>;
289317
#size-cells = <1>;
@@ -305,9 +333,10 @@
305333
pinctrl-0 = <&ps_hold_default_state>;
306334
};
307335

308-
sfpb_wrapper_mutex: syscon@1200000 {
309-
compatible = "syscon";
310-
reg = <0x01200000 0x8000>;
336+
sfpb_mutex: hwmutex@1200600 {
337+
compatible = "qcom,sfpb-mutex";
338+
reg = <0x01200600 0x100>;
339+
#hwlock-cells = <1>;
311340
};
312341

313342
intc: interrupt-controller@2000000 {
@@ -326,6 +355,8 @@
326355
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
327356
reg = <0x0200a000 0x100>;
328357
clock-frequency = <27000000>;
358+
clocks = <&sleep_clk>;
359+
clock-names = "sleep";
329360
cpu-offset = <0x80000>;
330361
};
331362

@@ -405,8 +436,8 @@
405436
};
406437
};
407438

408-
sps_sic_non_secure: sps-sic-non-secure@12100000 {
409-
compatible = "syscon";
439+
sps_sic_non_secure: interrupt-controller@12100000 {
440+
compatible = "qcom,apq8064-sps-sic", "syscon";
410441
reg = <0x12100000 0x10000>;
411442
};
412443

@@ -1089,7 +1120,7 @@
10891120
};
10901121

10911122
mmss_sfpb: syscon@5700000 {
1092-
compatible = "syscon";
1123+
compatible = "qcom,apq8064-mmss-sfpb", "syscon";
10931124
reg = <0x5700000 0x70>;
10941125
};
10951126

@@ -1532,39 +1563,6 @@
15321563
};
15331564
};
15341565

1535-
replicator {
1536-
compatible = "arm,coresight-static-replicator";
1537-
1538-
clocks = <&rpmcc RPM_QDSS_CLK>;
1539-
clock-names = "apb_pclk";
1540-
1541-
out-ports {
1542-
#address-cells = <1>;
1543-
#size-cells = <0>;
1544-
1545-
port@0 {
1546-
reg = <0>;
1547-
replicator_out0: endpoint {
1548-
remote-endpoint = <&etb_in>;
1549-
};
1550-
};
1551-
port@1 {
1552-
reg = <1>;
1553-
replicator_out1: endpoint {
1554-
remote-endpoint = <&tpiu_in>;
1555-
};
1556-
};
1557-
};
1558-
1559-
in-ports {
1560-
port {
1561-
replicator_in: endpoint {
1562-
remote-endpoint = <&funnel_out>;
1563-
};
1564-
};
1565-
};
1566-
};
1567-
15681566
funnel@1a04000 {
15691567
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
15701568
reg = <0x1a04000 0x1000>;

‎arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,6 @@
5353
reg = <0x0>;
5454
clocks = <&gcc GCC_APPS_CLK_SRC>;
5555
clock-frequency = <0>;
56-
clock-latency = <256000>;
5756
operating-points-v2 = <&cpu0_opp_table>;
5857
};
5958

@@ -67,7 +66,6 @@
6766
reg = <0x1>;
6867
clocks = <&gcc GCC_APPS_CLK_SRC>;
6968
clock-frequency = <0>;
70-
clock-latency = <256000>;
7169
operating-points-v2 = <&cpu0_opp_table>;
7270
};
7371

@@ -81,7 +79,6 @@
8179
reg = <0x2>;
8280
clocks = <&gcc GCC_APPS_CLK_SRC>;
8381
clock-frequency = <0>;
84-
clock-latency = <256000>;
8582
operating-points-v2 = <&cpu0_opp_table>;
8683
};
8784

@@ -95,7 +92,6 @@
9592
reg = <0x3>;
9693
clocks = <&gcc GCC_APPS_CLK_SRC>;
9794
clock-frequency = <0>;
98-
clock-latency = <256000>;
9995
operating-points-v2 = <&cpu0_opp_table>;
10096
};
10197

‎arch/arm/boot/dts/qcom/qcom-msm8226.dtsi

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
/dts-v1/;
77

88
#include <dt-bindings/interrupt-controller/arm-gic.h>
9+
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
910
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
1011
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
1112
#include <dt-bindings/clock/qcom,rpmcc.h>
@@ -1138,8 +1139,8 @@
11381139
<&gcc GPLL0_VOTE>,
11391140
<&gcc GPLL1_VOTE>,
11401141
<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1141-
<&mdss_dsi0_phy 1>,
1142-
<&mdss_dsi0_phy 0>;
1142+
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
1143+
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>;
11431144
clock-names = "xo",
11441145
"mmss_gpll0_vote",
11451146
"gpll0_vote",
@@ -1215,8 +1216,8 @@
12151216

12161217
assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
12171218
<&mmcc PCLK0_CLK_SRC>;
1218-
assigned-clock-parents = <&mdss_dsi0_phy 0>,
1219-
<&mdss_dsi0_phy 1>;
1219+
assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1220+
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
12201221

12211222
clocks = <&mmcc MDSS_MDP_CLK>,
12221223
<&mmcc MDSS_AHB_CLK>,

‎arch/arm/boot/dts/qcom/qcom-msm8974.dtsi

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33

44
#include <dt-bindings/interconnect/qcom,msm8974.h>
55
#include <dt-bindings/interrupt-controller/arm-gic.h>
6+
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
67
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
78
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
89
#include <dt-bindings/clock/qcom,rpmcc.h>
@@ -1871,10 +1872,10 @@
18711872
<&gcc GPLL0_VOTE>,
18721873
<&gcc GPLL1_VOTE>,
18731874
<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1874-
<&mdss_dsi0_phy 1>,
1875-
<&mdss_dsi0_phy 0>,
1876-
<&mdss_dsi1_phy 1>,
1877-
<&mdss_dsi1_phy 0>,
1875+
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
1876+
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1877+
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
1878+
<&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
18781879
<0>,
18791880
<0>,
18801881
<0>;
@@ -1961,8 +1962,10 @@
19611962
interrupt-parent = <&mdss>;
19621963
interrupts = <4>;
19631964

1964-
assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1965-
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1965+
assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1966+
<&mmcc PCLK0_CLK_SRC>;
1967+
assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1968+
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
19661969

19671970
clocks = <&mmcc MDSS_MDP_CLK>,
19681971
<&mmcc MDSS_AHB_CLK>,
@@ -2032,8 +2035,10 @@
20322035
interrupt-parent = <&mdss>;
20332036
interrupts = <4>;
20342037

2035-
assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
2036-
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2038+
assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2039+
<&mmcc PCLK1_CLK_SRC>;
2040+
assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
2041+
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;
20372042

20382043
clocks = <&mmcc MDSS_MDP_CLK>,
20392044
<&mmcc MDSS_AHB_CLK>,

‎arch/arm/boot/dts/qcom/qcom-sdx55.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@
5757
enable-method = "psci";
5858
clocks = <&apcs>;
5959
power-domains = <&rpmhpd SDX55_CX>;
60-
power-domain-names = "rpmhpd";
60+
power-domain-names = "perf";
6161
operating-points-v2 = <&cpu_opp_table>;
6262
};
6363
};

‎arch/arm/boot/dts/qcom/qcom-sdx65.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@
5858
enable-method = "psci";
5959
clocks = <&apcs>;
6060
power-domains = <&rpmhpd SDX65_CX_AO>;
61-
power-domain-names = "rpmhpd";
61+
power-domain-names = "perf";
6262
operating-points-v2 = <&cpu_opp_table>;
6363
};
6464
};

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