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Chao Haojoergroedel
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iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL
For iommu offset=0x48 register, only the previous mt8173/mt8183 use the name STANDARD_AXI_MODE, all the latest SoC extend the register more feature by different bits, for example: axi_mode, in_order_en, coherent_en and so on. So rename REG_MMU_MISC_CTRL may be more proper. This patch only rename the register name, no functional change. Signed-off-by: Chao Hao <[email protected]> Reviewed-by: Yong Wu <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
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2 files changed

+11
-8
lines changed

2 files changed

+11
-8
lines changed

drivers/iommu/mtk_iommu.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@
4141
#define F_INVLD_EN0 BIT(0)
4242
#define F_INVLD_EN1 BIT(1)
4343

44-
#define REG_MMU_STANDARD_AXI_MODE 0x048
44+
#define REG_MMU_MISC_CTRL 0x048
4545
#define REG_MMU_DCM_DIS 0x050
4646

4747
#define REG_MMU_CTRL_REG 0x110
@@ -573,8 +573,10 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
573573
}
574574
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
575575

576-
if (data->plat_data->reset_axi)
577-
writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
576+
if (data->plat_data->reset_axi) {
577+
/* The register is called STANDARD_AXI_MODE in this case */
578+
writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
579+
}
578580

579581
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
580582
dev_name(data->dev), (void *)data)) {
@@ -718,8 +720,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
718720
struct mtk_iommu_suspend_reg *reg = &data->reg;
719721
void __iomem *base = data->base;
720722

721-
reg->standard_axi_mode = readl_relaxed(base +
722-
REG_MMU_STANDARD_AXI_MODE);
723+
reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
723724
reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
724725
reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
725726
reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
@@ -743,8 +744,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
743744
dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
744745
return ret;
745746
}
746-
writel_relaxed(reg->standard_axi_mode,
747-
base + REG_MMU_STANDARD_AXI_MODE);
747+
writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
748748
writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
749749
writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
750750
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);

drivers/iommu/mtk_iommu.h

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,10 @@
1818
#include <soc/mediatek/smi.h>
1919

2020
struct mtk_iommu_suspend_reg {
21-
u32 standard_axi_mode;
21+
union {
22+
u32 standard_axi_mode;/* v1 */
23+
u32 misc_ctrl;/* v2 */
24+
};
2225
u32 dcm_dis;
2326
u32 ctrl_reg;
2427
u32 int_control0;

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