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17 | 17 | #include "clk-regmap-divider.h"
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18 | 18 | #include "clk-regmap-mux.h"
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19 | 19 | #include "clk-regmap-phy-mux.h"
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| 20 | +#include "gdsc.h" |
20 | 21 | #include "reset.h"
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21 | 22 |
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22 | 23 | enum {
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@@ -2409,6 +2410,39 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
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2409 | 2410 | },
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2410 | 2411 | };
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2411 | 2412 |
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| 2413 | +static struct gdsc pcie_0_gdsc = { |
| 2414 | + .gdscr = 0x9d004, |
| 2415 | + .en_rest_wait_val = 0x2, |
| 2416 | + .en_few_wait_val = 0x2, |
| 2417 | + .clk_dis_wait_val = 0xf, |
| 2418 | + .pd = { |
| 2419 | + .name = "gcc_pcie_0_gdsc", |
| 2420 | + }, |
| 2421 | + .pwrsts = PWRSTS_OFF_ON, |
| 2422 | +}; |
| 2423 | + |
| 2424 | +static struct gdsc pcie_0_phy_gdsc = { |
| 2425 | + .gdscr = 0x7c004, |
| 2426 | + .en_rest_wait_val = 0x2, |
| 2427 | + .en_few_wait_val = 0x2, |
| 2428 | + .clk_dis_wait_val = 0x2, |
| 2429 | + .pd = { |
| 2430 | + .name = "gcc_pcie_0_phy_gdsc", |
| 2431 | + }, |
| 2432 | + .pwrsts = PWRSTS_OFF_ON, |
| 2433 | +}; |
| 2434 | + |
| 2435 | +static struct gdsc usb30_prim_gdsc = { |
| 2436 | + .gdscr = 0x49004, |
| 2437 | + .en_rest_wait_val = 0x2, |
| 2438 | + .en_few_wait_val = 0x2, |
| 2439 | + .clk_dis_wait_val = 0xf, |
| 2440 | + .pd = { |
| 2441 | + .name = "gcc_usb30_prim_gdsc", |
| 2442 | + }, |
| 2443 | + .pwrsts = PWRSTS_OFF_ON, |
| 2444 | +}; |
| 2445 | + |
2412 | 2446 | static struct clk_regmap *gcc_qdu1000_clocks[] = {
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2413 | 2447 | [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr,
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2414 | 2448 | [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr,
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@@ -2545,6 +2579,12 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = {
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2545 | 2579 | [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr,
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2546 | 2580 | };
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2547 | 2581 |
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| 2582 | +static struct gdsc *gcc_qdu1000_gdscs[] = { |
| 2583 | + [PCIE_0_GDSC] = &pcie_0_gdsc, |
| 2584 | + [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc, |
| 2585 | + [USB30_PRIM_GDSC] = &usb30_prim_gdsc, |
| 2586 | +}; |
| 2587 | + |
2548 | 2588 | static const struct qcom_reset_map gcc_qdu1000_resets[] = {
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2549 | 2589 | [GCC_ECPRI_CC_BCR] = { 0x3e000 },
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2550 | 2590 | [GCC_ECPRI_SS_BCR] = { 0x3a000 },
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@@ -2606,6 +2646,8 @@ static const struct qcom_cc_desc gcc_qdu1000_desc = {
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2606 | 2646 | .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks),
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2607 | 2647 | .resets = gcc_qdu1000_resets,
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2608 | 2648 | .num_resets = ARRAY_SIZE(gcc_qdu1000_resets),
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| 2649 | + .gdscs = gcc_qdu1000_gdscs, |
| 2650 | + .num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs), |
2609 | 2651 | };
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2610 | 2652 |
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2611 | 2653 | static const struct of_device_id gcc_qdu1000_match_table[] = {
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